m368l1624dtl Samsung Semiconductor, Inc., m368l1624dtl Datasheet
m368l1624dtl
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m368l1624dtl Summary of contents
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... M368L1624DTL 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx16 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity 184pin Unbuffered DDR SDRAM MODULE Revision 0.1 May. 2002 Rev. 0.1 May. 2002 ...
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... M368L1624DTL Revision History Revision 0 (Jan. 2002) 1. First release for internal usage Revision 0.1 (May. 2002) 1.Change pin location of A13 from pin 103 to pin 167 184pin Unbuffered DDR SDRAM MODULE Rev. 0.1 May. 2002 ...
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... M368L1624DTL M368L1624DTL DDR SDRAM 184pin DIMM 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16 GENERAL DESCRIPTION The Samsung M368L1624DTL is 16M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsung M368L1624DTL consists of four CMOS 16M x 16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP- II(400mil) packages mounted on a 184pin glass-epoxy sub- strate ...
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... M368L1624DTL FUNCTIONAL BLOCK DIAGRAM CS0 DQS1 LDQS CS DM1 LDM DQ8 I/O 6 DQ9 I DQ10 I/O 1 DQ11 I/O 3 DQ12 I/O 2 DQ13 I/O 0 DQ14 I/O 5 DQ15 I/O 7 DQS0 UDQS DM0 UDM DQ0 I/O 8 DQ1 I/O 10 DQ2 I/O 15 DQ3 I/O 13 DQ4 I/O 12 DQ5 I/O 14 DQ6 I/O 11 DQ7 I/O 9 DQS3 CS LDQS DM3 LDM DQ24 I/O 6 DQ25 I DQ26 I/O 1 DQ27 I/O 3 DQ28 I/O 2 DQ29 ...
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... M368L1624DTL Absolute Maximum Rate Parameter Voltage on any pin relative to V Voltage on V & V supply relative DDQ Storage temperature Power dissipation Short circuit current Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... M368L1624DTL DDR SDRAM module IDD spec table Symbol B3(DDR333@CL=2.5) IDD0 360 IDD1 500 IDD2P 12 IDD2F 100 IDD2Q 80 IDD3P 140 IDD3N 220 IDD4R 800 IDD4W 760 IDD5 720 Normal 12 IDD6 Low power 6 IDD7A 1400 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. ...
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... M368L1624DTL Output Input/Output CAPACITANCE Parameter Input capacitance Input capacitance(CKE ) 0 Input capacitance Input capacitance( CLK , CLK ) 1 2 Data & DQS input/output capacitance(DQ Input capacitance(DM ~ 184pin Unbuffered DDR SDRAM MODULE V =0.5*V tt DDQ R =50 T Z0=50 C =30pF LOAD Output Load Circuit (SSTL_2 ...
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... M368L1624DTL AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2 ...
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... M368L1624DTL Parameter Symbol Mode register set cycle time tMRD DQ & DM setup time to DQS tDS DQ & DM hold time to DQS tDH Control & Address input pulse width tIPW DQ & DM input pulse width tDIPW Power down exit time tPDEX Exit self refresh to non-Read command ...
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... M368L1624DTL 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 This derating table is used to increase t is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V ...
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... M368L1624DTL Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...
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... M368L1624DTL PACKAGE DIMENSIONS 1.25 (31.75 0.250 (6.350) 0.26 (6.62) 2.175 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 16Mx16 DDR SDRAM, TSOP. SDRAM Part NO : K4H561638D 184pin Unbuffered DDR SDRAM MODULE 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) A 2.55 (64.77) (49.53) 0.157 (4.00) 0.1496 (3.80) 0.071 (1.80 ) (1.270) Detail B Units : Inches (Millimeters) ...