m368l1624dtl Samsung Semiconductor, Inc., m368l1624dtl Datasheet - Page 5

• Manufacturer Part Number: m368l1624dtl
• Description: 16mx64 Ddr Sdram 184pin Dimm Based On 16mx16
• Manufacturer: Samsung Semiconductor, Inc.

Notes 1. Includes 25mV margin for DC offset on V
Recommended operating conditions(Voltage referenced to V
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
M368L1624DTL
Absolute Maximum Rate
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Supply voltage(for device with a nominal V
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
Output High Current(Normal strengh driver)
Output High Current(Half strengh driver)
Output High Current(Half strengh driver)
;V
;V
;V
;V
OUT
OUT
OUT
OUT
2.V
3. V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
5. The value of V
6. These charactericteristics obey the SSTL-2 class II standards.
Voltage on V
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
TO V
V
= V
= V
= V
= V
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
TT
REF
I D
T T
T T
is not applied directly to the device. V
Voltage on any pin relative to V
T T
T T
is the magnitude of the difference between the input level on CK and the input level on CK.
, and must track variations in the DC level of V
REF
+ 0.84V
+ 0.45V
- 0.84V
- 0.45V
, both of which may result in V
Storage temperature
D D
Short circuit current
Power dissipation
Parameter
& V
IX
Parameter
is expected to equal 0.5*V
DDQ
supply relative to V
SS
DD
REF
of 2.5V)
T T
SS
noise. V
REF
DDQ
is a system supply for signal termination resistors, is expected to be set equal to
184pin Unbuffered DDR SDRAM MODULE
, and a combined total of
of the transmitting device and must track variations in the dc level of the same.
REF
REF
SS
Symbol
V
V
V
V
V
=0V, T
V
V
I H
IL
I N
I D
IX
V
V
should be de-coupled with an inductance of
I
I
I
I
I
DDQ
REF
(DC)
O Z
OH
OL
OH
OL
V
(DC)
(DC)
(DC)
(DC)
DD
I
V
TT
I
Symbol
DD
I N
T
, V
I
P
, V
STG
OS
A
D
=0 to 70 C)
OUT
DDQ
VDDQ/2-50mV
V
V
REF
REF
-16.8
Min
1.15
16.8
-0.3
-0.3
2.3
2.3
0.3
-2
-5
-9
9
+0.15
-0.04
50mV margin for all AC noise and DC offset on V
-55 ~ +150
-0.5 ~ 3.6
-1.0 ~ 3.6
VDDQ/2+50mV
Value
50
V
6
V
V
V
V
REF
REF
DDQ
REF
DDQ
DDQ
Max
1.35
2.7
2.7
2
5
+0.04
-0.15
and internal DRAM noise coupled
+0.3
+0.3
+0.6
Rev. 0.1 May. 2002
3nH.
Unit
mA
mA
mA
mA
uA
uA
V
V
V
V
V
V
V
V
Unit
mA
W
V
V
C
Note
1
2
4
4
3
5
REF
,