m393t2863az3 Samsung Semiconductor, Inc., m393t2863az3 Datasheet - Page 4

• Manufacturer Part Number: m393t2863az3
• Description: Ddr2 Registered Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

DDR2 Registered DIMM Ordering Information
Features
Address Configuration
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Note: "A" of Part number(12th digit) stand for Parity Register products.
M393T2863AZ3-CD5/CC
M393T2863AZA-CE6/D5/CC
M393T5663AZ3-CD5/CC
M393T5663AZA-CE6/D5/CC
M393T5660AZ3-CD5/CC
M393T5660AZA-CE6/D5/CC
M393T5168AZ0-CD5/CC
M393T5166AZA-CE6/D5/CC
1GB, 2GB, 4GB Registered DIMMs
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
• 200 MHz f
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8 (Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 68ball FBGA - 256Mx4/128Mx8, 56ball BGA - st.512Mbx4
• All of Lead-free products are compliant for RoHS
-
DDQ
support High Temperature Self-Refresh rate enable feature
256Mx4(1Gb) based Module
128Mx8(1Gb) based Module
CL-tRCD-tRP
Speed@CL3
Speed@CL4
Speed@CL5
Part Number
= 1.8V ± 0.1V
Organization
CK
for 400Mb/sec/pin, 267MHz f
Density
E6(DDR2-667)
1GB
1GB
2GB
2GB
2GB
2GB
4GB
4GB
5-5-5
400
533
667
Organization
128Mx72
128Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
Row Address
CK
A0-A13
A0-A13
for 533Mb/sec/pin, 333MHz f
CASE
D5(DDR2-533)
85qC, 3.9us at 85qC < T
st.512Mx4(K4T2G064QA)*18EA
st.512Mx4(K4T2G264QA)*18EA
128Mx8(K4T1G084QA)*18EA
128Mx8(K4T1G084QA)*18EA
256Mx4(K4T1G044QA)*18EA
256Mx4(K4T1G044QA)*18EA
128Mx8(K4T1G084QA)*9EA
128Mx8(K4T1G084QA)*9EA
4-4-4
Component Composition
400
533
533
Column Address
A0-A9, A11
A0-A9
CK
CC(DDR2-400)
CASE
for 667Mb/sec/pin
3-3-3
400
400
-
< 95 qC
Bank Address
Number of Rank
BA0-BA2
BA0-BA2
.
1
1
2
2
1
1
2
2
Mbps
Mbps
Mbps
Unit
CK
Rev. 1.2 Sep. 2005
DDR2 SDRAM
Parity Register
Auto Precharge
O
O
O
O
X
X
X
X
A10
A10
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm