m393t6553bg Samsung Semiconductor, Inc., m393t6553bg Datasheet - Page 15

• Manufacturer Part Number: m393t6553bg
• Description: Ddr2 Registered Sdram Module 240pin Registered Module Based On 512mb B-die 72-bit Ecc
• Manufacturer: Samsung Semiconductor, Inc.

Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
Refresh Parameters by Device Density
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Refresh to active/Refresh command time
Average periodic refresh interval
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
tRP
tRC
tRAS
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
512MB, 1GB, 2GB Registered DIMMs
(0 qC < T
Parameter
Speed
CASE
< 95 qC; V
Parameter
DDQ
= 1.8V + 0.1V; V
tRFC
tREFI
3.75
min
15
15
55
40
5
-
DDR2-533(D5)
DD
85qC T
4 - 4 - 4
0qCdT
= 1.8V + 0.1V)
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
Symbol
CASE
CASE
70000
max
8
8
d 85qC
-
d 95qC
min(tCL, tCH)
tHP - tQHS
2* tACmin
WL-0.25
tAC min
3750
min
0.45
0.45
0.35
0.35
-500
-450
225
100
0.35
0.6
x
x
x
DDR2-533
256Mb
7.8
3.9
75
tAC max
WL+0.25
tAC max
tAC max
max
min
+500
+450
8000
0.55
0.55
15
15
55
40
300
400
5
5
-
x
x
x
x
x
x
x
x
512Mb
DDR2-400(CC)
105
7.8
3.9
3 - 3 - 3
min(tCL, tCH)
tHP - tQHS
2* tACmin
WL-0.25
tAC min
5000
min
-600
-500
0.45
0.45
0.35
0.35
0.35
275
150
0.6
x
x
x
DDR2-400
127.5
1Gb
7.8
3.9
Rev. 1.3 Aug. 2005
70000
max
8
8
DDR2 SDRAM
-
WL+0.25
tAC max
tAC max
tAC max
max
+600
+500
0.55
0.55
8000
350
450
x
x
x
x
x
x
x
x
2Gb
195
7.8
3.9
Units
4Gb
tbd
7.8
3.9
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Units
ns
ns
ns
ns
ns
ns
ns
Notes
Units
ns
Ps
Ps