m470l3224bt0 Samsung Semiconductor, Inc., m470l3224bt0 Datasheet

no-image

m470l3224bt0

Manufacturer Part Number
m470l3224bt0
Description
256mb Ddr Sdram Module
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
M470L3224BT0
200pin DDR SDRAM SODIMM
256MB DDR SDRAM MODULE
(32Mx64 based on 16Mx16 DDR SDRAM)
200pin SODIMM
64-bit Non-ECC/Parity
Revision 0.1
June. 2001
Rev. 0.1 June. 2001

Related parts for m470l3224bt0

m470l3224bt0 Summary of contents

Page 1

... M470L3224BT0 256MB DDR SDRAM MODULE (32Mx64 based on 16Mx16 DDR SDRAM) 64-bit Non-ECC/Parity 200pin DDR SDRAM SODIMM 200pin SODIMM Revision 0.1 June. 2001 Rev. 0.1 June. 2001 ...

Page 2

... M470L3224BT0 Revision History Revision 0.0 (Apr. 2001) 1. First release. Revision 0.1 (June. 2001) 1. Changed module current speificaton 2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm). 3. Changed AC parameter table. 200pin DDR SDRAM SODIMM Rev. 0.1 June. 2001 ...

Page 3

... M470L3224BT0 200pin DDR SDRAM SODIMM 32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16 GENERAL DESCRIPTION The Samsung M470L3224BT0 is 32M bit x 64 Double Data Rate SDRAM high density memory modules based on first gen of 256Mb DDR SDRAM respectively. The Samsung M470L3224BT0 consists of eight CMOS 16M x ...

Page 4

... M470L3224BT0 FUNCTIONAL BLOCK DIAGRAM S1 S0 DQS0 LDQS S DM0 LDM DQ0 I/0 0 DQ1 I/0 1 DQ2 I DQ3 I/0 3 DQ4 I/0 4 DQ5 I/0 5 DQ6 I/0 6 DQ7 I/0 7 DQS1 UDQS DM1 UDM DQ0 I/0 8 DQ1 I/0 9 DQ2 I/0 10 DQ3 I/0 11 DQ4 I/0 12 DQ5 I/0 13 DQ6 I/0 14 DQ7 I/0 15 DQS2 LDQS S DM2 LDM DQ0 I/0 0 DQ1 I/0 1 DQ2 I DQ3 I/0 3 DQ4 I/0 4 DQ5 ...

Page 5

... M470L3224BT0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...

Page 6

... M470L3224BT0 DDR SDRAM SPEC Items and Test Conditions Recommended operating conditions Unless Otherwise Noted, T Conditions Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ...

Page 7

... M470L3224BT0 DDR SDRAM module I spec table DD A2(DDR266@CL=2) Symbol typical IDD0 620 IDD1 760 IDD2P 320 IDD2F 380 IDD2Q 360 IDD3P 380 IDD3N 440 IDD4R 1080 IDD4W 1280 IDD5 960 Normal 24 IDD6 Low power 12 IDD7A 1700 I * Module was calculated on the basis of component DD < ...

Page 8

... M470L3224BT0 DD7A I : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ Worst Case : Vdd = 2.7V, T= 10’ Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge ...

Page 9

... M470L3224BT0 AC OPERATING TEST CONDITIONS Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output Input/Output CAPACITANCE Parameter Input capacitance Input capacitance(CKE ...

Page 10

... M470L3224BT0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2 ...

Page 11

... M470L3224BT0 Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active command Exit self refresh to read command 64Mb, 128Mb ...

Page 12

... M470L3224BT0 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 This derating table is used to increase t based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 This derating table is used to increase t based on the lesser of AC-AC slew rate and DC-DC slew rate. ...

Page 13

... M470L3224BT0 Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...

Page 14

... M470L3224BT0 PACKAGE DIMENSIONS 0.16 0.039 (4.00 0.10) 1 0.086 0.456 2.15 11.40 0.07 (1.8) 0.098 2.45 2 0.150 Max (3.80 Max) 0.04 0.0039 (1.00 0.10) Tolerances : .006(.15) unless otherwise specified The used device is 16Mx16 SDRAM, TSOP SDRAM Part No. : K4H561638B-TC/L 200pin DDR SDRAM SODIMM 2.70 (67.60) 2.50 (63.60 1.896 (47.40) 0.17 (4.20) 0.096 (2.40 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z Units : Inches (Millimeters) Full R 2x 199 2- 0 ...

Related keywords