m470l3224bt0 Samsung Semiconductor, Inc., m470l3224bt0 Datasheet - Page 7

• Manufacturer Part Number: m470l3224bt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM module I
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
4. Timing patterns
* Module
M470L3224BT0
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
IDD6
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
Symbol
IDD4W
IDD2P
IDD2Q
IDD3P
IDD3N
IDD4R
IDD7A
IDD2F
IDD0
IDD1
IDD5
I
DD
Low power
Normal
was calculated on the basis of component
typical
A2(DDR266@CL=2)
1080
1280
1700
620
760
320
380
360
380
440
960
DD
24
12
spec table
worst
1240
1460
1080
1940
680
840
340
420
380
400
480
24
12
B0(DDR266@CL=2.5)
typical
1080
1280
1700
620
760
320
380
360
380
440
960
I
24
12
DD
and can be differently measured according to DQ loading cap.
worst
1240
1460
1080
1940
680
840
340
420
380
400
480
24
12
200pin DDR SDRAM SODIMM
A0(DDR200@CL=2)
typical
1000
1420
540
680
260
320
300
320
360
900
880
24
12
worst
1040
1140
1640
600
760
280
340
320
340
380
960
24
12
Rev. 0.1 June. 2001
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Optional
Notes