m470l3224dt0 Samsung Semiconductor, Inc., m470l3224dt0 Datasheet - Page 10

• Manufacturer Part Number: m470l3224dt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

M470L3224DT0
8. I/O Setup/Hold Plateau Derating
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF
This derating table is used to increase t
up to 2ns.
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
(Single ended)
CK slew rate
Delta Rise/Fall Rate
0.75V/ns
1.0V/ns
0.5V/ns
I/O Input Level
(ns/V)
(mV)
0.25
0.5
280
0
tIH/tIS
+100
(ps)
+50
0
DS
/t
+100
(ps)
+50
(ps)
+50
DH
tDS
tDS
0
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
tDSS/tDSH
+100
(ps)
+50
0
+100
(ps)
+50
(ps)
+50
tDH
tDH
0
tAC/tDQSCK
+100
(ps)
+50
0
200pin DDR SDRAM SODIMM
tLZ(min)
-100
(ps)
-50
0
310mV for a duration of
tHZ(max)
Rev. 0.1 Jan. 2002
+100
(ps)
+50
0