m470l3224dt0 Samsung Semiconductor, Inc., m470l3224dt0 Datasheet - Page 5

• Manufacturer Part Number: m470l3224dt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

Notes 1. Includes
Recommended operating conditions(Voltage referenced to V
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
M470L3224DT0
Absolute Maximum Rate
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Supply voltage(for device with a nominal V
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
Output High Current(Normal strengh driver)
Output High Current(Half strengh driver)
Output High Current(Half strengh driver)
;V
;V
;V
;V
OUT
OUT
OUT
OUT
2.V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
5. The value of V
6. These charactericteristics obey the SSTL-2 class II standards.
3. V
Voltage on V
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
TO V
V
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
= V
= V
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
= V
= V
TT
REF
ID
TT
TT
is not applied directly to the device. V
TT
TT
is the magnitude of the difference between the input level on CK and the input level on CK.
, and must track variations in the DC level of V
REF
Voltage on any pin relative to V
+ 0.84V
+ 0.45V
- 0.84V
- 0.45V
, both of which may result in V
25mV margin for DC offset on V
Storage temperature
DD
Short circuit current
Power dissipation
Parameter
IX
& V
Parameter
is expected to equal 0.5*V
DDQ
supply relative to V
DD
SS
REF
of 2.5V)
TT
noise. V
SS
REF
DDQ
is a system supply for signal termination resistors, is expected to be set equal to
, and a combined total of 50mV margin for all AC noise and DC offset on V
of the transmitting device and must track variations in the dc level of the same.
REF
REF
SS
Symbol
V
V
V
V
V
V
=0V, T
V
IH
IL
IN
ID
IX
V
V
should be de-coupled with an inductance of
I
I
I
I
I
DDQ
REF
(DC)
OZ
OH
OH
(DC)
OL
OL
(DC)
(DC)
(DC)
DD
I
TT
I
V
V
Symbol
DD
IN
T
A
, V
I
, V
P
STG
OS
=0 to 70 C)
D
OUT
DDQ
VDDQ/2-50mV
V
V
REF
REF
200pin DDR SDRAM SODIMM
-16.8
Min
1.15
16.8
-0.3
-0.3
2.3
2.3
0.3
-2
-5
-9
9
+0.15
-0.04
-55 ~ +150
-0.5 ~ 3.6
-1.0 ~ 3.6
VDDQ/2+50mV
Value
V
V
V
V
V
12
50
REF
REF
REF
DDQ
DDQ
DDQ
Max
1.35
2.7
2.7
2
5
+0.04
-0.15
and internal DRAM noise coupled
+0.3
+0.3
+0.6
Rev. 0.1 Jan. 2002
3nH.
Unit
mA
mA
mA
mA
uA
uA
V
V
V
V
V
V
V
V
Unit
mA
W
V
V
C
Note
1
2
4
4
3
5
REF
,