m470l6524fl0 Samsung Semiconductor, Inc., m470l6524fl0 Datasheet - Page 4

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m470l6524fl0

Manufacturer Part Number
m470l6524fl0
Description
200pin Unbuffered Sodimm Based On 512mb F-die
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.0 Ordering Information
Note:
1. “L” and “6” of part number(11th digit) stand for Lead-Free, Halogen-Free, and RoHS compliant products.
2.0 Operating Frequencies
3.0 Feature
• V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height - 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil)
• SSTL_2 Interface
• 66pin TSOP II & 54pin sTSOP II package
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
512MB, 1GB Unbuffered SODIMM
DD
Speed @CL2.5
: 2.5V ± 0.2V, V
CL-tRCD-tRP
M470L6524FL0-C(L)B3
M470L2923F60-C(L)B3
Part Number
200Pin Unbuffered SODIMM based on 512Mb F-die (x8, x16)
DDQ
: 2.5V ± 0.2V for DDR333
Density
512MB
1GB
Organization
2 of 15
128M x 64
64M x 64
B3(DDR333@CL=2.5)
166MHz
2.5-3-3
64Mx8 (K4H510838F) * 16EA
32Mx16 (K4H511638F) * 8EA
Component Composition
Rev. 1.01 August 2008
DDR SDRAM
1,250mil
1,250mil
Height

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