m470t6464az3 Samsung Semiconductor, Inc., m470t6464az3 Datasheet - Page 16

• Manufacturer Part Number: m470t6464az3
• Description: Ddr2 Unbuffered Sodimm 200pin Unbuffered Sodimm Based On 1gb A-die 64-bit Non-ecc
• Manufacturer: Samsung Semiconductor, Inc.

13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
SODIMM
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for
each input
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK/CK tHZ
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ
signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated
clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB
page size products
Active to active command period for 2KB
page size products
Four Activate Window for 1KB page size
products
Four Activate Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Internal read to precharge command delay tRTP
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tXSNR
tXSRD
tXP
Symbol
tHP - tQHS
tRFC + 10
2*tACmin
WR+tRP
min(tCL,
tAC min
3000
-0.25
-400
tCH)
min
0.45
0.45
0.35
0.35
0.35
37.5
-450
175
100
0.35
275
200
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
7.5
15
x
2
2
2
x
x
DDR2-667
16 of 20
tAC max
tAC max
tAC max
+400
8000
max
0.55
0.55
0.25
+450
240
0.6
1.1
0.6
340
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tHP - tQHS
tRFC + 10
2* tACmin
WR+tRP
min(tCL,
tAC min
-0.25
3750
0.45
0.45
tCH)
0.35
0.35
37.5
min
-500
-450
225
100
0.35
375
250
200
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
10
50
15
2
2
2
x
x
x
DDR2-533
tAC max
tAC max
tAC max
+500
+450
8000
max
0.55
0.55
0.25
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tHP - tQHS
2* tACmin
tRFC + 10
WR+tRP
min(tCL,
tAC min
5000
-0.25
-600
-500
tCH)
0.45
0.45
0.35
0.35
0.35
37.5
min
275
150
0.35
475
350
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
15
10
x
2
2
2
x
x
DDR2-400
Rev. 1.4 March 2007
DDR2 SDRAM
tAC max
tAC max
tAC max
+600
+500
max
0.55
0.55
8000
0.25
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
Note