hys64t128021edl-25fb2 Qimonda, hys64t128021edl-25fb2 Datasheet - Page 17

• Manufacturer Part Number: hys64t128021edl-25fb2
• Description: 200-pin So-dimm Ddr2 Sdram Modules Ddr2 Sdram
• Manufacturer: Qimonda

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
Rev. 1.20, 2008-06
08212006-PKYN-2H1B
Parameter
Control & address input pulse width
for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from
CK / CK
MRS command to ODT update delay
Mode register set command cycle
time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Read preamble
Read postamble
Active to active command period for
1KB page size products
Active to active command period for
2KB page size products
Internal Read to Precharge command
delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
Exit self-refresh to a non-read
command
Exit self-refresh to read command
Write command to DQS associated
clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
QHS
REFI
RFC
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
DDR2–800
0.6
175
2 x
t
0
2
0
t
—
—
—
105
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
Min.
AC.MIN
HP
RFC
–
t
AC.MIN
+10
t
QHS
17
Max.
—
—
t
t
12
—
12
—
300
7.8
3.9
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
AC.MAX
AC.MAX
HYS64T[64/128]02xEDL–[25F/2.5/3S](–)B2
DDR2–667
0.6
200
2 x
t
0
2
0
t
—
—
—
105
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
7 – AL
2
t
200
RL–1
Min.
AC.MIN
HP
RFC
Small Outlined DDR2 SDRAM Modules
–
t
AC.MIN
+10
t
QHS
Max.
—
—
t
t
12
—
12
—
340
7.8
3.9
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
AC.MAX
AC.MAX
Internet Data Sheet
Unit
t
ps
ps
ps
ns
nCK
ns
ps
ps
μs
μs
ns
t
t
ns
ns
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Note
)4)5)6)7)
23)24)
8)21)
8)21)
34)
34)
25)
26)
27)28)
27)29)
30)
31)32)
31)33)
34)
34)
34)
34)
34)35)
34)
1)2)3