m391t2953cz3-ce7 Samsung Semiconductor, Inc., m391t2953cz3-ce7 Datasheet - Page 17

• Manufacturer Part Number: m391t2953cz3-ce7
• Description: Ddr2 Unbuffered Sdram Module 240pin Unbuffered Module Based On 512mb C-die 64/72-bit Non-ecc/ecc
• Manufacturer: Samsung Semiconductor, Inc.

Electrical Characteristics & AC Timing for DDR2-800/667/533/400
Refresh Parameters by Device Density
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
256MB, 512MB, 1GB Unbuffered DIMMs
Parameter
Refresh to active/Refresh command time
Average periodic refresh interval
Bin
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
tRP
tRC
tRAS
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each
input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ
signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
DQS input high pulse width
DQS input low pulse width
(CL - tRCD - tRP)
(0 qC < T
Speed
Parameter
OPER
< 95 qC; V
3.75
12.5
12.5
51.5
min
2.5
39
DDR2-800(E7)
5
DDQ
5 - 5 - 5
= 1.8V + 0.1V; V
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
Symbol
70000
max
Symbol
tRFC
tREFI
8
8
8
-
-
-
min(tCL,t
tAC min
2* tAC
- 0.25
tQHS
2500
tHP -
min
- 400
- 350
0.45
0.45
CH)
0.35
0.35
125
0.35
min
50
0.6
0qCdT
85qC T
DDR2-800
x
x
x
3.75
min
15
15
54
39
DD
DDR2-667(E6)
5
3
= 1.8V + 0.1V)
5 - 5 - 5
tAC max
tAC max
tAC max
CASE
max
8000
0.55
0.55
0.25
200
300
CASE
400
350
x
x
x
x
x
x
x
x
d 85qC
d 95qC
70000
max
8
8
8
min(tCL,
-
-
-
tAC min
2*tAC
tQHS
tHP -
-0.25
tCH)
3000
min
-400
0.45
0.45
0.35
0.35
-450
175
100
0.35
min
0.6
DDR2-667
x
x
x
tAC max
tAC max
tAC max 2* tACmin tAC max 2* tACmin
max
+400
8000
3.75
3.75
0.55
0.55
0.25
min
+450
340
240
15
15
55
40
256Mb
DDR2-533(D5)
x
x
5
x
x
x
x
x
x
7.8
3.9
75
4 - 4 - 4
min(tCL,
tAC min
tQHS
3750
tHP -
-0.25
min
tCH)
0.45
0.45
0.35
0.35
-500
-450
225
100
0.35
0.6
x
DDR2-533
x
x
512Mb
70000
max
105
7.8
3.9
8
8
8
-
-
-
tAC max
tAC max
max
+500
+450
8000
0.55
0.55
0.25
300
400
x
x
x
x
x
x
x
x
127.5
1Gb
7.8
3.9
min
15
15
55
40
DDR2-400(CC)
min(tCL,
Rev. 1.2 Aug. 2005
5
5
-
tAC min
tHP -
tQHS
-0.25
5000
min
-600
-500
0.45
0.45
tCH)
0.35
0.35
0.35
275
150
0.6
x
x
x
3 - 3 - 3
DDR2-400
DDR2 SDRAM
2Gb
195
7.8
3.9
tAC max
tAC max
tAC max
70000
max
+600
+500
max
0.55
0.55
8000
0.25
350
450
x
x
8
8
-
-
-
-
x
x
x
x
x
x
327.5
4Gb
7.8
3.9
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Ps
Ps
Note