mt9vddf6472y-335 Micron Semiconductor Products, mt9vddf6472y-335 Datasheet
mt9vddf6472y-335
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mt9vddf6472y-335 Summary of contents
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... DDR SDRAM REGISTERED DIMM Features • 184-pin, dual, in-line memory module (DIMM) • Fast data transfer rates: PC1600, PC2100, or PC2700 • Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components • Registered Inputs with one-clock delay • Phase-lock loop (PLL) clock driver to reduce loading • ...
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... MT9VDDF3272G-262__ MT9VDDF3272Y-262__ 256MB MT9VDDF3272G-26A__ 256MB 256MB MT9VDDF3272Y-26A__ 256MB MT9VDDF3272(I)G-265__ MT9VDDF3272(I)Y-265__ 256MB MT9VDDF3272(I)G-202__ 256MB MT9VDDF3272(I)Y-202__ 256MB 512MB MT9VDDF6472G-335__ MT9VDDF6472Y-335__ 512MB MT9VDDF6472G-262__ 512MB MT9VDDF6472Y-262__ 512MB 512MB MT9VDDF6472G-26A__ 512MB MT9VDDF6472Y-26A__ MT9VDDF6472(I)G-265__ 512MB MT9VDDF6472(I)Y-265__ 512MB 512MB MT9VDDF6472(I)G-202__ 512MB ...
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... V SS A12 138 CK0# 161 DQ46 No Components This Side of Module PIN 145 PIN 144 No Components This Side of Module PIN 145 PIN 144 U12 U13 PIN 145 PIN 144 pin SS Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 10 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, 59 ...
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... Supply Ground. SS Supply Serial EEPROM positive power supply: . DDSPD DNU — Do Not Use: Thes pins are not connected on these modules, but are assigned pins on other modules in this product family NC — No Connect: These pins should be left unconnected. 5 256MB, 512MB (x72, ECC, SR) ...
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... RRAS#: DDR SDRAMs S RCAS#: DDR SDRAMs T RCKE0: DDR SDRAMs E RWE#: DDR SDRAMs R S RESET# Standard modules use the following DDR SDRAM devices: Lead-free modules use the following DDR SDRAM devices: www.micron.com/num- 6 256MB, 512MB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM DM CS# DQS DQ DQ32 DQ DQ33 DQ ...
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... RRAS#: DDR SDRAMs S RCAS#: DDR SDRAMs T RCKE0: DDR SDRAMs E RWE#: DDR SDRAMs R S RESET# Standard modules use the following DDR SDRAM devices: Lead-free modules use the following DDR SDRAM devices: www.micron.com/num- 7 256MB, 512MB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM DM CS# DQS DQ DQ32 DQ DQ33 DQ ...
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... RCKE0: DDR SDRAMs RWE#: DDR SDRAMs RESET Standard modules use the following DDR SDRAM devices: MT46V32M8FG (256MB); MT46V64M8FG (512MB) Lead-free modules use the following DDR SDRAM devices: www.micron.com/num- MT46V32M8BG (256MB); MT46V64M8BG (512MB) Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 ...
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... I/O pins. A single read or write access for the DDR SDRAM module effec- tively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data trans- fers at the I/O pins ...
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Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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DLL should always be followed by a LOAD MODE REGISTER command to the mode regis- ter (BA0/BA1 both LOW) to ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- Voltage on V ...
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Table 12: IDD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 20–23; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); ...
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Table 13: IDD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 20–23; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 14: Capacitance Note: 11; notes appear on pages 20–23 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 8, 10, 12; notes appear on pages 20–23; 0°C AC CHARACTERISTICS PARAMETER DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1–5, 8, 10, 12; notes appear on pages 20–23; 0°C AC CHARACTERISTICS PARAMETER Address and control input hold time (slow slew rate) Address ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid ...
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READs and WRITEs with auto precharge are not t allowed to be issued until RAS(MIN) can be satis- fied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than ...
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... DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... Timing and switching specifications for the register listed above are critical for proper operation of DDR SDRAM Regis- tered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. ...
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... Timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed informa- tion for this PLL is available in JEDEC Standard JESD82. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Fig- ure 13, Data Validity, and Figure 14, Definition ...
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Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read ...
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Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage 3mA ...
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... Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Banks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels t 9 SDRAM Cycle Time, CK (CAS Latency = 2.5) (See note 1) 10 SDRAM Access From Clock, (CAS Latency = 2.5) ...
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... SPD Revision 63 Checksum For Bytes 0–62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continued) 93 Year of Manufacture in BCD pdf: 09005aef80e119b2, source: 09005aef807d56a1 DDF9C32_64x72G.fm - Rev. B 9/04 EN 256MB, 512MB (x72, ECC, SR) ...
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... The value of RAS used for -26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is repesented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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... U10 U4 U8 0.035 (0.90) R 0.040 (1.02) 0.250 (6.35) TYP. TYP. 1.95 (49.53) 4.750 (120.65) BACK VIEW No Components This Side of Module MAX or typical where noted. MIN Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 184-PIN DDR SDRAM RDIMM 0.700 (17.78) TYP. U10 0.394 (10.00) TYP ...
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Figure 19: 184-PIN DIMM Dimensions – Very Low-Profile .00) R (4X 2.50) D (2X) 30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. PIN 184 Data Sheet Designation Released (No Mark): This data sheet ...