mt2ldt432h Micron Semiconductor Products, mt2ldt432h Datasheet - Page 12

• Manufacturer Part Number: mt2ldt432h
• Description: Small-outline Dram Module Technology
• Manufacturer: Micron Semiconductor Products

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10.For FPM: If CAS# = V
11.If CAS# = V
12.Measured with a load equivalent to two TTL gates
13.If CAS# is LOW at the falling edge of RAS#, Q will
14.The
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
rates. Specified values are obtained with minimum
cycle time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range is ensured.
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
t
measuring timing of input signals. Transition times
are measured between V
and V
specification, all input signals must transit between
V
tonic manner.
For EDO: If CAS# and RAS# = V
High-Z.
the last valid READ cycle.
and 100pF, V
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
REF refresh requirement is exceeded.
T = 2.5ns for EDO.
RCD was greater than the specified
DD
IH
IH
is dependent on output loading and cycle
(MIN) and V
and V
t
RCD (MAX) limit is no longer specified.
IH
).
IL
(or between V
IL
, data output may contain data from
OL
= 0.8V and V
IL
(MAX) are reference levels for
IH
, data output is High-Z.
IH
IL
t
t
and V
CP.
T = 5ns for FPM and
SS
and V
DD
.
OH
= +3.3V; f = 1 MHz.
IL
= 2V.
IH
IH
, data output is
(or between V
) in a mono-
t
RCD (MAX)
t
RCD
IL
12
15.The
16.Either
17.
18.These parameters are referenced to CAS# leading
19.OE# is tied permanently LOW; LATE WRITE or
20.A HIDDEN REFRESH may also be performed after
21.The 3ns minimum is a parameter guaranteed by
22.Column address changed once each cycle.
23.With the FPM option,
24.Applies to both FPM and EDO operating modes.
25.“S” version only.
26.V
by
without the
must always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
or without the
t
cycle.
t
achieves the open circuit condition and is not
referenced to V
edge in EARLY WRITE cycles.
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
a WRITE cycle. In this case, WE# = LOW and OE#
= HIGH.
design.
first RAS# or CAS# signal to transition HIGH. In
comparison,
mined by the latter of the RAS# and CAS# signals
to transition HIGH.
width £ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
undershoot: V
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
RAD was greater than the specified
CAC must always be met.
OFF (MAX) defines the time at which the output
IH
t
t
CAC (
AA (
overshoot: V
t
RAD (MAX) limit is no longer specified.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCH or
t
RAC and
t
RAC [MIN] no longer applied). With or
t
t
RCD (MAX) limit,
OFF on an EDO option is deter-
IL
OH
t
t
RRH must be satisfied for a READ
RAD (MAX) limit,
(MIN) = -2V for a pulse width £
IH
or V
t
(MAX) = V
CAC no longer applied). With
DRAM SODIMMs
OL
t
OFF is determined by the
.
4, 8 MEG x 32
DD
t
AA and
+ 2V for a pulse
t
AA,
©1998, Micron Technology, Inc.
t
RAD (MAX)
ADVANCE
t
RAC and
t
IL
CAC
t
RAD