atr0625p ATMEL Corporation, atr0625p Datasheet
atr0625p
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atr0625p Summary of contents
Page 1
... Core Supply Voltage • Includes Power Supervisor • 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance • 4 Kbytes Battery Backup Memory • Pin QFN56 Package • RoHS-compliant, Green ® Processor Core GPS Baseband Processor SuperSense ATR0625P 4925F–GPS–09/07 ...
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... A-GPS (aiding also possible to store the configuration settings in an optional external EEPROM. The ATR0625P is manufactured using Atmel the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide range of peripheral functions on a monolithic chip, the ATR0625P provides a highly flexible and cost-effective solution for GPS applications. ATR0625P 2 ® ...
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... Figure 1-1. ATR0625P Block Diagram NSHDN NSLEEP XT_IN XT_OUT RF_ON CLK23 P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM DBG_EN NTRST TDI TDO TCK TMS NRESET 4925F–GPS–09/07 ATR0625P ...
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... As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0625P peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space ...
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... Pin Configuration 3.1 Pinout Figure 3-1. Pinout QFN56 (Top View) Table 3-1. ATR0625P Pinout Pin Name QFN56 Pin Type CLK23 37 OUT DBG_EN 8 IN (2) GND IN LDOBAT_IN 21 IN LDO_EN 25 IN LDO_IN 20 IN LDO_OUT 19 OUT NRESET 41 I/O NSHDN 26 OUT NSLEEP 24 OUT NTRST ...
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... Table 3-1. ATR0625P Pinout (Continued) Pin Name QFN56 Pin Type P14 1 I/O P15 17 I/O P16 6 I/O P17 2 I/O P18 45 I/O P19 53 I/O P20 4 I/O P21 52 I/O P22 30 I/O P23 3 I/O P24 5 I/O P25 55 I/O P26 44 I/O P27 54 I/O P29 50 I/O P30 16 I/O P31 31 I/O RF_ON 15 OUT SIGHI0 38 IN SIGLO0 39 IN TCK 9 IN TDI 10 IN TDO 11 OUT TMS 12 IN USB_DM ...
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... Signal Description Table 3-2. ATR0625P Signal Description Module Name Function EBI BOOT_MODE Boot Mode Input TXD1 to TXD2 Transmit Data Output USART RXD1 to RXD2 Receive Data Input SCK1 to SCK2 External Synchronous Serial Clock USB_DP USB Data (D+) USB USB_DM USB Data (D-) APMC RF_ON AIC ...
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... Table 3-2. ATR0625P Signal Description (Continued) Module Name Function TMS Test Mode Select TDI Test Data In TDO Test Data Out JTAG/ICE TCK Test Clock NTRST Test Reset Input DBG_EN Debug Enable CLOCK CLK23 Clock Input RESET NRESET Reset Input VDD18 VDDIO POWER ...
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... GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0625P can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0) ...
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... Serial I/O Configuration The ATR0625P features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port ...
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... Part of Output Data) Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST Proprietary PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, NAV VELNED, TIMEGPS, TIMEUTC, CLOCK MON SCHD, IO, IPC, EXCEPT RXM RAW (RAW message support requires an additional license) ATR0625P 11 ...
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... P15/ANTON assumed that also input P25/NAADET0/MISO will signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see page ATR0625P 12 Serial I/O Default Setting if GPSMODE Configuration is Deselected (GPSMODE0 = 0) ...
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... Low = Power supply to active antenna is switched off Comment P25/NAADET0/MISO P25/NAADET0/MISO Reserved for further use. P14/NAADET1 Do not use this setting. P14/NAADET1 (Default ROM value) Reserved for further use. P14/NAADET1 Do not use this setting. Reserved for further use. P14/NAADET1 Do not use this setting. P25/NAADET0/MISO P25/NAADET0/MISO ATR0625P 13 ...
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... TMS NC TCK NC TDI NC NTRST NC TDO NC DBG_EN GND GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18 VBAT +3V ATR0625P P8 STATUS LED P20 TIMEPULSE USB_DM Optional USB_DP USB P31 Optional USART 1 P18 P22 Optional USART 2 P21 XT_IN 32.368 kHz (see RTC) XT_OUT +3V (see Power Supply) ...
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... GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page ATR0625P ...
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... Connecting an Optional Serial EEPROM The ATR0625P offers the possibility to connect an external serial EEPROM. The internal ROM firmware supports to store the configuration of the ATR0625P in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0625P. The 32-bit RISC processor of the ATR0625P accesses the external memory with SPI (Serial Peripheral Interface) ...
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... In input mode, the four GPIO-pins are 5V input tolerant. Figure Figure 4-1. 2.3V to 3.6V 4925F–GPS–09/07 4-1, Figure 4-2, and Figure 4-3 show examples of the wiring of ATR0625P power supply. External Wiring Example Using Internal LDOs and Backup Power Supply NSHDN 1 µF (X7R) 1.5V to 3.6V 1 µF (X7R 3.6V ...
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... SRAM from any input voltage LDOBAT_IN between 2.3V and 3.6V or from VBAT between 1.5V and 3.6V. The backup battery connected to VBAT is only discharged if the supply connected to LDOBAT_IN is shut-down. Only after VDD18 has been supplied to ATR0625P the RTC section will be initialized properly. If only VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. ...
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... External USB-VSB 5V LDO 3.3V 4925F–GPS–09/07 LDO_IN NSHDN LDO_EN LDO_OUT VDD18 1 µF (X7R) VDDIO LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 1 µF (X7R) VDDUSB ATR0625P ATR0625P internal LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable IO Domain LDOBAT ldobat_in vbat vbat18 vdd RTC Backup Memory USB SM and Transceiver 19 ...
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... VDD_USB LDO_IN LDOBAT_IN VBAT P0, P15, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP P1, P2, P8, P9, P12 to P14, P16 to P27, P29, P31 Symbol R thJA ATR0625P internal RTC Min. Max. Unit –40 +85 °C –60 +150 °C –0.3 +1.95 V – ...
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... Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT 4925F–GPS–09/07 Pin VDD18 VDDIO VDD_USB VBAT18 CLK23 CLK23 CLK23 NRESET NRESET P9, P13, P22, P31 P9, P13, P22, P31 DP 1.5 mA, VDD18 = = –1.5 mA, = 1.5 mA, VDDIO = ATR0625P Symbol Min. Typ. Max. VDD18 1.65 1.8 1.95 VDDIO 1.65 1.8/3.3 3.6 VDDUSB 3.0 3.3 3.6 VBAT18 1.65 1.8 1.95 ...
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... VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT ATR0625P 22 Pin = –1.5 mA, VDDIO = ...
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... Sleep Shutdown Normal *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 10. ESD Sensitivity The ATR0625P is an ESD sensitive device. The current ESD values are to be defined. Observe precautions for handling. Table 10-1. Test Model Human Body Model (HBM) 11. LDO18 The LDO18 is a built in low dropout voltage regulator which can be used if the host system does not provide the core voltage VDD18 ...
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... Current consumption LDOBAT_IN Current consumption (1) VBAT Current consumption *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: ATR0625P 24 Electrical Characteristics of LDOBAT Conditions After startup (sleep/backup mode), at (1) room temperature After startup (backup mode and LDOBAT_IN = 0V), at room temperature ...
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... Moisture sensitivity level (MSL 4925F–GPS–09/07 Package MPQ QFN56 2000 - 0.9 max. +0 0.05 -0.05 Remarks mm, 0.50 mm pitch, RoHS-compliant, green Evaluation kit/Road test kit Development kit including example design information 8 6 0.5 nom. ATR0625P Pin 1 ID technical drawings according to DIN specifications 25 ...
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... ATR0625P 26 History Table 3-1 “ATR0625P Pinout” on page 5 changed Section 8 “Table Electrical Characteristics” numbers 1.35 and 1.36 on page 22 changed All pages: Part number changed in ATR0625P Page 20: Abs. Max. Ratings table: some changes Page 21-22: El. Characteristics table: Type column added Page 23: Power Consumption table: Type column added ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. ARM Ltd ...