psd511b1 STMicroelectronics, psd511b1 Datasheet - Page 151

• Manufacturer Part Number: psd511b1
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMicroelectronics

21.0
Process
Change Notice,
October 1, 1998
148
PSD5XX Family
PSD5XX Functional Change:
A change has been implemented in the most recent silicon that improves the way that the
Image Register is updated. This change only applies to Event Count Mode for counter units
CTU0, CTU1, and CTU3.
Previous PSD5XX Silicon:
The Image Register was not updated with the actual event count upon exiting Freeze
mode. As a result, in certain circumstances, the Image Register may not have reflected the
actual event count. Although an incorrect count may have been read from the Image
Register at a given time, no event counts were ever lost because the microcontroller would
eventually read the correct value in the Image Register on subsequent freeze and read
cycles.
Current PSD5XX Silicon:
The Image register is now automatically updated with the actual count upon exiting the
Freeze mode. This ensures that on the very next freeze and read cycle, the microcontroller
will read the actual count from the Image register. There are two restrictions however:
1. If an event occurs within one timer clock period plus two CLKIN periods after the image
2. The time between an unfreeze and the beginning of the next freeze has the same time
To reduce the chance of getting a delayed count in the Image Register due to restriction
number 1, execute a software Load/Store command just prior to freezing and reading the
Image Register to force an update to the Image count.
Backwards Compatibility:
This improvement should have no impact on current designs unless these designs
were compensating for lost events. In such cases, compatibility is dependent on the
compensation method that was used. Please contact WSI at [e-mail] if you
think you have an issue or have any questions.
register is unfrozen, then the Image Register will not reflect that event on the very next
freeze and read cycle (timer clock period is defined on page 6-79 of the 1996 PSD data
book). Instead, the event will appear in the Image Register on the subsequent freeze
and read cycle.
constraint as number one. There must be at least one timer clock period plus two CLKIN
periods between the end of one freeze cycle and the beginning of the next. This timing
can be controlled by software design.