ppc440epx Applied Micro Circuits Corporation (AMCC), ppc440epx Datasheet - Page 56

• Manufacturer Part Number: ppc440epx
• Description: Powerpc 440epx Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

440EPx – PPC440EPx Embedded Processor
of the external bus, these same pins are used as inputs which are driven by the external master and received by
the EBC in the PPC440EPx. In this example, the pins are also bidirectional, serving both as inputs and outputs.
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 90). Note that
these are not multiplexed pins since the function of the pins is not programmable.
Unused I/Os
Termination of unused receivers is generally required; however, there are some exceptions that reduce or
eliminate the need for termination.
Signals Multiplexed with GPIO:
56
By default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however,
is not needed if the GPIO during initialization are configured as outputs. To configure as drivers, set and clear
the appropriate bits in the GPIOx_ODR, GPIOx_TCR and GPIOx_OR registers as described in the GPIO
chapter of the user’s manual.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReg0[Gnt}
signal low. Parking forces the PLB3 to PCI bridge to actively drive PCIAD31:0 and PCIC3:0[BE3:0]. The
remaining PCI control signals must be terminated as follows:
DDR:
GMII and MII:
SMIIx
RGMIIx
Note:
terminating an unused PCI interface).
– Disable the internal PCI arbiter and enable PCI synchronous mode. (See IIC Boot Strap Chapter in the
– Individually connect PCISErr, PCITRDY, and PCIStop through 3k
– Individually connect PCIReq1:5 through 3k
– Connect PCIReq0[Gnt] through 1k
– In 32 bit mode, termination is not needed on the upper data, strobe and mask signals when the DDR
– Termination of unused ECC signals (ECC0:7, DM8, DQS8) is not needed.
– Configure EMAC0 and EMAC1 to use internal clocks by setting SDR0_MFR[EnCS]=1 and reset
– Pull down the following signals with 1K resistor: GMCRefClk, GMCCD, GMCTxCLK and GMCRxClk.
– Configure the unused EMACn to use an internal clock by setting SDR0_MFR[EnCS]=1 and reset
– No pull ups or pull downs required.
– Configure the unused EMACn to use an internal clock by setting SDR0_MFR[EnCS]=1 and reset
– Pull down the unused GMCnRxClk signal with a 1K resistor. Pull down is only required if the interface
user’s manual).
I/O and DDR controller are configured for 32 bit mode, SDR0_DDRCFG[64B32B]=0 and
DDR0_14[REDUC]=1.
EMACn by setting EMACn_MR0[SRST]=1.
Pull downs are only required if the interface is never used.
EMACn by setting EMACn_MR1[SRST]=1.
EMACn by setting EMACn_MR1[SRST]=1
is never used.
Synchronous mode is not supported when operating the PCI bus. (This mode should only be used for
Ω
resistor to GND.
Ω
resistors to +3.3V.
Ω
Preliminary Data Sheet
resistors to +3.3V.
Revision 1.29 – July 22, 2008
AMCC Proprietary