ppc440epx Applied Micro Circuits Corporation (AMCC), ppc440epx Datasheet - Page 57

• Manufacturer Part Number: ppc440epx
• Description: Powerpc 440epx Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

Revision 1.29 – July 22, 2008
Table 8. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
Preliminary Data Sheet
PCI Interface
PCIAD00:31
PCIC0:3/BE0:3
PCIClk
PCIDevSel
PCIFrame
PCIGnt0/Req
PCIGnt1:5
PCIIDSel
PCIINT
PCIIRDY
PCIPar
PCIPErr
PCIReq0/Gnt
PCIReq1:5
PCIReset
PCISErr
PCIStop
PCITRDY
Signal Name
Address/Data bus (bidirectional).
Provides timing to the PCI interface for PCI transactions.
Even parity.
PCI Command/Byte Enables
Indicates the driving device has decoded its address as the
target of the current access.
(PCI 2.2 specification requires 8.2K
Driven by the current master to indicate beginning and duration
of an access.
(PCI 2.2 specification requires 8.2K
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is PCIGnt0. When
the internal arbiter is disabled, output is Req.
Indicates that the specified agent is granted access to the bus.
Used only when internal PCI arbiter enabled.
Used as a chip select during configuration read and write
transactions.
Level sensitive PCI interrupt.
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2K
Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires 8.2K
Indicates to the PCI arbiter that the specified agent wishes to use
the bus. When the internal arbiter is enabled, input is PCIReq0.
When internal arbiter is disabled, input is Gnt.
An indication to the PCI arbiter that the specified agent wishes to
use the bus. Used only when internal PCI arbiter enabled.
Brings PCI device registers and logic to a consistent state.
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires 8.2K
Indicates the current target is requesting the master to stop the
current transaction.
(PCI 2.2 specification requires 8.2K
I
phase of the transaction.
(PCI 2.2 specification requires 8.2K
ndicates the target agent’s ability to complete the current data
DD
(EOV
Description
.
DD
DD
for Ethernet)
440EPx – PPC440EPx Embedded Processor
Ω
Ω
Ω
Ω
Ω
Ω
Ω
(EOV
pull up on host system)
pull up on host system)
pull up on host system)
pull up on host system)
pull up on host system)
pull up on host system)
pull up on host system)
DD
for Ethernet)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Type
Notes
1, 5
1, 4
1, 4
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