ppc405cr Applied Micro Circuits Corporation (AMCC), ppc405cr Datasheet - Page 26

• Manufacturer Part Number: ppc405cr
• Description: Powerpc 405cr Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PPC405CR – PowerPC 405CR Embedded Processor
Table 6. Signal Functional Description (Sheet 4 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
26
Interrupts Interface
JTAG Interface
System Interface
IRQ0:6[GPIO17:23]
[UART1_CTS]
[UART1_DTR]
UART1_DSR/
UART1_RTS/
Signal Name
UART1_Tx
SysReset
IICSDA
IICSCL
SysClk
SysErr
TRST
TMS
TDO
TCK
Halt
TDI
UART1 Transmit (serial data out).
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must toggle
a DCR register bit.
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR register bit.
IIC serial clock.
IIC serial data.
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR register bit.
Test data in.
JTAG test mode select.
Test data out.
JTAG test clock. The frequency of this input can range from DC to
25MHz.
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405CR.
Main system clock input.
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states, 0 or open circuit).
Set to 1 when a Machine Check is generated.
Halt from external debugger.
Description
Revision 1.02 – January 11, 2005
I[I/O]
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
Data Sheet
Notes
1, 2
1, 2
1, 4
1, 4
1, 4
1, 2
1, 2
6
1
6
1
5
AMCC