ppc405cr Applied Micro Circuits Corporation (AMCC), ppc405cr Datasheet - Page 27

• Manufacturer Part Number: ppc405cr
• Description: Powerpc 405cr Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PPC405CR – PowerPC 405CR Embedded Processor
Table 6. Signal Functional Description (Sheet 5 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
AMCC
Power
Other pins
GPIO5:8[TS3:6]
GPIO9[TrcClk]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO1[TS1E]
GPIO2[TS2E]
Signal Name
DrvrInh1:2
Reserved
RcvrInh
TestEn
TmrClk
OV
AV
GND
V
DD
DD
DD
General Purpose I/O
or
Even Trace execution status. To access this function, software must
toggle a DCR register bit.
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR register bit.
General Purpose I/O
Trace status. To access this function, software must toggle a DCR
register bit.
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
register bit.
Test Enable.
Receiver Inhibit. Used only for manufacturing tests. Pull up for normal
operation.
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for
normal operation.
An external clock input than can be used as an alternative to SysClk
to run the CPU core. Which clock input is used is determined by
software settings.
Ground
Note: Pins J9–J12, K9–K12, L9–L12, and M9–M12 are also thermal
balls.
Filtered voltage input for PLL (analog) circuits
Output driver voltage—3.3V
Logic voltage—2.5V
Connect G19 to GND. Do not connect signals, voltage, or ground to
any other reserved pins.
Description
Revision 1.02 – January 11, 2005
I/O[O]
I/O[O]
I/O[O]
I/O[O]
I/O
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-down
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
Data Sheet
Notes
1, 6
1, 6
1
1
2
2
1
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