54abt273 National Semiconductor Corporation, 54abt273 Datasheet

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54abt273

Manufacturer Part Number
54abt273
Description
Octal D-type Flip-flop
Manufacturer
National Semiconductor Corporation
Datasheet

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© 1998 National Semiconductor Corporation
54ABT273
Octal D-Type Flip-Flop
General Description
The ’ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n Eight edge-triggered D flip-flops
Ordering Code
TRI-STATE
54ABT273J-QML
54ABT273W-QML
54ABT273E-QML
®
is a registered trademark of National Semiconductor Corporation.
Military
J20A
W20A
E20A
DS100205
Package
Number
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
n Buffered common clock
n Buffered, asynchronous Master Reset
n See ’ABT377 for clock enable version
n See ’ABT373 for transparent latch version
n See ’ABT374 for TRI-STATE
n Output sink capability of 48 mA, source capability of
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
n Non-destructive hot insertion capability
n Disable time less than enable time to avoid bus
n Standard Microcircuit Drawing (SMD) 5962-9321701
24 mA
power up and power down cycle
contention
Package Description
®
version
www.national.com
July 1998

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54abt273 Summary of contents

Page 1

... Eight edge-triggered D flip-flops Ordering Code Military Package Number 54ABT273J-QML J20A 54ABT273W-QML W20A 54ABT273E-QML E20A TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100205 n Buffered common clock n Buffered, asynchronous Master Reset n See ’ABT377 for clock enable version n See ’ ...

Page 2

Connection Diagrams Pin Assignment for DIP and Flatpack DS100205-1 Truth Table Mode Select-Function Table Operating Mode Inputs MR CP Reset (Clear Load “1” Load “0” H Logic Diagram Please note that this diagram is provided ...

Page 3

Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input ...

Page 4

AC Electrical Characteristics Symbol Parameter f Max Clock max Frequency t Propagation Delay PLH PHL n t Propagation Delay PHL Operating Requirements Symbol Parameter t (H) Setup Time, HIGH s t ...

Page 5

AC Loading DS100205-4 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Propagation Delay, Pulse Width Waveforms FIGURE 3. V Input Pulse Requirements Amplitude Rep. Rate 3.0V 1 MHz FIGURE 4. Test Input Signal Requirements DS100205-5 ...

Page 6

6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 7 www.national.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR ...

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