adsst-21065lks-240 Analog Devices, Inc., adsst-21065lks-240 Datasheet - Page 10

• Manufacturer Part Number: adsst-21065lks-240
• Description: High End, Multichannel, 32-bit Floating-point Audio Processor
• Manufacturer: Analog Devices, Inc.

SST-Melody-SHARC
Mnemonic
TCK
TMS
TDI
TDO
TRST
EMU (O/D)
BMSTR
CAS
RAS
SDWE
DQM
SDCLK1–0
SDCKE
SDA10
XTAL
PWM_EVENT1–0 I/O/A
VDD
GND
NC
I = Input, S = Synchronous, P = Power Supply, (O/D) = Open Drain, O = Output, A = Asynchronous, G = Ground, (A/D) = Active Drive, T = Three-state
(when SBTS is asserted, or when the SST-Melody-SHARC is a bus slave).
Type
I
I/S
I/S
O
I/A
O
O
I/O/T
I/O/T
I/O/T
O/T
I/O/S/T
I/O/T
O/T
O
P
G
Function
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up
resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal
pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up
or held low for proper operation of the SST-Melody-SHARC. TRST has a 20 kΩ internal pull-up
resistor.
Emulation Status. Must be connected to the SST-Melody-SHARC EZ-ICE target board connector
only.
Bus Master Output. In a multiprocessor system, indicates whether the SST-Melody-SHARC is cur-
rent bus master of the shared external bus. The SST-Melody-SHARC drives BMSTR high only while
it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high.
SDRAM Column Access Strobe. Provides the column address. In conjunction with RAS, MSx,
SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Row Access Strobe. Provides the row address. In conjunction with CAS, MSx, SDWE,
SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used to block write operations.
SDRAM 2× Clock Output. In systems with multiple SDRAM devices connected in parallel, supports
the corresponding increased clock load requirements, eliminating need of off-chip clock buffers.
Either SDCLK1 or both SDCLKx pins can be three-stated.
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied
with your SDRAM device.
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a host access.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the SST-Melody-SHARC’s inter-
nal clock generator or to disable it to use an external clock source. See CLKIN.
PWM Output/Event Capture. In PWMOUT mode, is an output pin and functions as a timer counter.
In WIDTH_CNT mode, is an input pin and functions as a pulse counter/event capture.
Power Supply; nominally 3.3 V dc (33 pins)
Power Supply Return (37 pins)
Do Not Connect. Reserved pins that must be left open and unconnected (7).
PIN FUNCTION DESCRIPTIONS (continued)
–10–
REV. 0