adsst-21065lks-240 Analog Devices, Inc., adsst-21065lks-240 Datasheet - Page 13

• Manufacturer Part Number: adsst-21065lks-240
• Description: High End, Multichannel, 32-bit Floating-point Audio Processor
• Manufacturer: Analog Devices, Inc.

Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all perform
single-cycle instructions. The three units are arranged in parallel,
maximizing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier operations.
These computation units support IEEE 32-bit single-precision
floating-point, extended precision 40-bit floating-point, and
32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the databuses, and for storing
intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the SST-Melody-SHARC
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The SST-Melody-SHARC features an enhanced Super Harvard
Architecture in which the data memory (DM) bus transfers data
and the program memory (PM) bus transfers both instructions
and data. With its separate program and data memory buses and
on-chip instruction cache, the processor can simultaneously
fetch two operands and an instruction (from the cache), all in a
single cycle.
Instruction Cache
The SST-Melody-SHARC includes an on-chip instruction cache
that enables 3-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions that
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates, and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The SST-Melody-SHARC’s two data address generators
(DAGs) implement circular data buffers in hardware. Circular
buffers allow efficient programming of delay lines and other data
structures required in digital signal processing, and are commonly
used in digital filters and Fourier transforms. The SST-Melody-
SHARC’s two DAGs contain sufficient registers to allow the
creation of up to 32 circular buffers (16 primary register sets, 16
secondary). The DAGs automatically handle address pointer
wraparound, reducing overhead, increasing performance, and
simplifying implementation. Circular buffers can start and end
at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the SST-
Melody-SHARC can conditionally execute a multiply, an add, a
subtract, and a branch all in a single instruction.
SST-MELODY-SHARC FEATURES
The SST-Melody-SHARC is designed to achieve the highest system
throughput to enable maximum system performance. It can be
clocked by either a crystal or a TTL-compatible clock signal.
The SST-Melody-SHARC uses an input clock with a frequency
equal to half the instruction rate—a 33 MHz input clock yields a
15 ns processor cycle (which is equivalent to 66 MHz). Interfaces
on the SST-Melody-SHARC operate as shown. Hereafter in this
document, 1× = input clock frequency and
2× = processor’s instruction rate.
REV. 0
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The following clock operation ratings are based on 1× = 33 MHz
(instruction rate/core = 66 MHz):
SST-Melody-SHARC adds the following architectural features:
Dual-Ported On-Chip Memory
The SST-Melody-SHARC contains 544 Kbits of on-chip
SRAM organized into two banks: Bank 0 has 288 Kbits, and
Bank 1 has 256 Kbits. Bank 0 is configured with nine columns
of 2K
umns of 2K
single-cycle, independent accesses by the core processor and I/O
processor or DMA controller. The dual-ported memory and
separate on-chip buses allow two data transfers from the core
and one from I/O, all in a single cycle (see Figure 4 for the SST-
Melody-SHARC Memory Map).
On the SST-Melody-SHARC, the memory can be configured as
a maximum of 16K words of 32-bit data, 34K words for 16-bit
data, 10K words of 48-bit instructions (and 40-bit data) or combi-
nations of different word sizes up to 544 Kbits. All the memory
can be accessed as 16-bit, 32-bit, or 48-bit.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data using
the DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers. Using the DM and PM
buses in this way, with one dedicated to each memory block,
assures single-cycle execution with two data transfers. In this case,
the instruction must be available in the cache. Single cycle execu-
tion is also maintained when one of the data operands is transferred
to or from off-chip, via the SST-Melody-SHARC’s external port.
Off-Chip Memory and Peripherals Interface
The SST-Melody-SHARC’s external port provides the
processor’s interface to off-chip memory and peripherals. The
64 M-word’s, off-chip address space is included in the SST-
Melody-SHARC’s unified address space. The separate on-chip
buses—for program memory, data memory, and I/O—are multi-
plexed at the external port to create an external system bus with
a single 24-bit address bus, four memory selects, and a single
32-bit databus. The on-chip Super Harvard Architecture provides
3-bus performance, while the off-chip unified address space
gives flexibility to the designer.
SDRAM Interface
The SDRAM interface enables the SST-Melody-SHARC to
transfer data to and from synchronous DRAM (SDRAM) at 2
clock frequency. The synchronous approach coupled with 2
clock frequency supports data transfer at a high throughput—up
to 220 Mbytes/sec.
The SDRAM interface provides a glueless interface with standard
SDRAMs—16 Mbyte, 64 Mbyte, and 128 Mbyte—and includes
options to support additional buffers between the SST-Melody-SHARC
and SDRAM. The SDRAM interface is extremely flexible and
provides capability for connecting SDRAMs to any one of
the SST-Melody-SHARC’s four external memory banks.
SDRAM
External SRAM
Serial Ports
Multiprocessing
Host (Asynchronous)
16 bits, and Bank 1 is configured with eight col-
16 bits. Each memory block is dual-ported for
SST-Melody-SHARC
66 MHz
33 MHz
33 MHz
33 MHz
33 MHz