m366s3354bts-c7a Samsung Semiconductor, Inc., m366s3354bts-c7a Datasheet - Page 15

• Manufacturer Part Number: m366s3354bts-c7a
• Description: Sdram Unbuffered Module 168pin Unbuffered Module Based On 512mb B-die 62/72-bit Non Ecc/ecc
• Manufacturer: Samsung Semiconductor, Inc.

AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
256MB, 512MB, 1GB Unbuffered DIMM
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
870:
Parameter
Parameter
3.3V
1200:
50pF
CAS latency=3
CAS latency=2
V
V
OH
OL
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
t
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
CCD
Symbol
t
RAS
RDL
CDL
DAL
BDL
DD
RC
RP
(min)
(min)
= 3.3V r0.3V, T
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
OL
OH
= 2mA
= -2mA
A
= 0 to 70qC)
See Fig. 2
tr/tf = 1/1
2.4/0.4
2 CLK + tRP
Value
1.4
1.4
Version
Output
100
7A
15
20
20
45
65
2
1
1
1
2
1
(Fig. 2) AC output load circuit
Rev. 1.1 February 2004
Z0 = 50:
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ea
-
SDRAM
Vtt = 1.4V
Unit
50:
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4