m366s3354bts-c7a Samsung Semiconductor, Inc., m366s3354bts-c7a Datasheet - Page 5

• Manufacturer Part Number: m366s3354bts-c7a
• Description: Sdram Unbuffered Module 168pin Unbuffered Module Based On 512mb B-die 62/72-bit Non Ecc/ecc
• Manufacturer: Samsung Semiconductor, Inc.

PIN CONFIGURATION DESCRIPTION
256MB, 512MB, 1GB Unbuffered DIMM
CLK
CS
CKE
A0 ~ A12
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
REGE
DQ0 ~ 63
CB0 ~ 7
V
DD
/V
Pin
SS
System clock
Chip select
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Register enable
Data input/output
Check bit
Power supply/ground
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x8 : CA0 ~ CA9, CA11), (x16 : CA0 ~ CA9)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power and ground for the input buffers and the core logic.
SHZ
after the clock and masks the output.
Input Function
Rev. 1.1 February 2004
DD
through 10K ohm
SDRAM