hdmp-1636 Avago Technologies, hdmp-1636 Datasheet - Page 6

• Manufacturer Part Number: hdmp-1636
• Description: Gigabit Ethernet Transceiver Chip
• Manufacturer: Avago Technologies

 
HDMP-1636/46 (Receiver Section)
Timing Characteristics
T
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
Figure 5. Receiver Section Timing.
Figure 6. Receiver Latency.
716
RX[0]-RX[9]
A
BYTSYNC
(defined as the first edge of the first serial) and the clocking out of that parallel word (defined by the rising edge of the receive byte
clock, either RBC1 or RBC0).
= 0 C to +70 C, V
b_sync
t
RBC1
RBC0
valid_before
t
t_rxlat
Symbol
valid_after
t
t
duty
t
A-B
valid_before


 
[1,2]
[3]
PLL
= 0.1 F.
K28.5
CC
Bit Sync Time
Time Data Valid Before Rising Edge of RBC
Time Data Valid After Rising Edge of RBC
RBC Duty Cycle
Rising Edge Time Difference
Receiver Latency
= 3.15 V to 3.45 V

 
t
valid_after
DATA
Parameter


 
DATA

 
DATA
Units
nsec
nsec
nsec
nsec
bits
bits
%

 
DATA
Min.
2.5
1.5
7.5
40
t
A-B
Typ.
TBD
TBD
22.4
7.9
28
1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
1.4 V
Max.
2500
8.5
60