cym1836v33 Cypress Semiconductor Corporation., cym1836v33 Datasheet - Page 4

• Manufacturer Part Number: cym1836v33
• Description: 128k 3.3v Static Module
• Manufacturer: Cypress Semiconductor Corporation.

Switching Characteristics
Switching Waveforms
Read Cycle No. 2
Read Cycle No.1
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Shaded area contains advance information.
Parameter
Notes:
WC
SCS
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
10. Address valid prior to or coincident with CS transition LOW.
7.
8.
9.
DATA OUT
DATA OUT
ADDRESS
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = V
OE
CS
Write Cycle
Time
CS LOW to Write
End
Address Set-Up
to Write End
Address Hold
from Write End
Address Set-Up
to Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to Low
Z
WE LOW to High
Z
[6]
Description
[7]
[8, 9]
[8, 10]
PREVIOUS DATA VALID
HIGH IMPEDANCE
t
LZCS
1836V33–15 1836V33–20 1836V33–25 1836V33–30 1836V33–35 1836V33–45
Min.
15
12
12
12
Over the Operating Range
0
0
7
0
3
0
IL
t
ACS
t
and OE= V
LZOE
PRELIMINARY
Max.
t
OHA
7
t
DOE
IL
Min.
.
20
15
15
15
10
0
0
0
3
0
t
AA
Max.
8
t
RC
[4]
Min.
4
25
15
15
15
10
(continued)
0
0
0
3
0
t
RC
Max.
10
DATA VALID
Min.
30
18
18
18
13
0
0
0
3
0
Max.
15
Min.
35
20
20
20
15
DATA VALID
0
0
0
3
0
t
HZOE
Max.
t
HZCS
15
CYM1836V33
Min.
45
25
25
25
20
0
0
0
3
0
IMPEDANCE
HIGH
Max.
18
1836V33–6
1836V33–7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns