hcts193ms Intersil Corporation, hcts193ms Datasheet

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hcts193ms

Manufacturer Part Number
hcts193ms
Description
Rad-hard Synchronous 4-bit Up/down Counter
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS193MS is a Radiation Hardened 4-bit binary
UP/DOWN synchronous counter.
Presetting the counter to the number on the preset data inputs
(P0 - P3) is accomplished by a low on the asynchronous parallel
load input (PL). The counter is incremented on the low to high
transition of the clock-up input (high on the clock-down),
decremented on the low to high transition of the clock-down input
(high on the clock-up). A high level on the MR input overrides any
other input to clear the counter to zero. The Terminal Count Up
goes low half a clock period before the zero count is reached and
returns high at the maximum count. The Terminal Count Down
mode goes low half a clock period before the maximum count
and returns high at the maximum count.
The HCTS193MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS193MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS193DMSR
HCTS193KMSR
HCTS193D/Sample
HCTS193K/Sample
HCTS193HMSR
Day (Typ)
- Standard Outputs - 10 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
-55
-55
RAD (Si)/s
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/Bit-
592
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS193MS
Synchronous 4-Bit Up/Down Counter
SCREENING LEVEL
Pinouts
GND
CPD
CPU
Q1
Q0
Q2
Q3
P1
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
CPD
CPU
Q1
Q0
Q2
Q3
MIL-STD-1835 CDFP4-F16
P1
MIL-STD-1835 CDIP2-T16
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
File Number
PACKAGE
P0
MR
TCD
TCU
PL
P2
P3
VCC
518620
3066.1
P0
MR
TCD
TCU
PL
P2
P3
VCC

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hcts193ms Summary of contents

Page 1

... The HCTS193MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS193MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...

Page 2

... CPU FF0 CPD 8 GND 16 VCC 3 Q0 FUNCTION CLOCK UP Count Up Count Down H Reset X Load Preset Inputs High Level Low Level Immaterial, HCTS193MS FF1 FF2 TRUTH TABLE CLOCK DOWN H ...

Page 3

... VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.8V (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS193MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... TSU VCC = 4. Hold Time TH VCC = 4. Hold Time CPD to TH VCC = 4.5V CPU or CPU to CPD Pulse Width TW VCC = 4.5V CPU to CPD Pulse Width PL TW VCC = 4.5V Specifications HCTS193MS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 10, 11 +125 9 10, 11 +125 9 10, 11 +125 9 10, 11 ...

Page 5

... VCC = 4. TPHL VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS193MS CONDITIONS NOTES TEMPERATURE 1 1 +125 1 1 +125 ...

Page 6

... Each pin except VCC and GND will have a resistor of 10K 2. Each pin except VCC and GND will have a resistor of 1K OPEN 12, 13 NOTE: Each pin except VCC and GND will have a resistor of 47K E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS193MS GROUP B SUBGROUP 5 5 TABLE 6. APPLICABLE SUBGROUPS ...

Page 7

... Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HCTS193MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs. min., o +125 C min., Method 1015 ...

Page 8

... FIGURE 5. SETUP AND HOLD TIMES DATA TO PARALLEL LOAD (PL) AC Timing Diagrams AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS193MS INPUT LEVEL VS CPU OR CPD VS TPHL TPLH TCU OR TCD VS FIGURE 2. CLOCK TO TERMINAL COUNT DELAYS INPUT LEVEL MR INPUT LEVEL VS TREC INPUT CPU OR CPD ...

Page 9

... Metallization Mask Layout Q0(3) CPD(4) CPU(5) Q2(6) Q3(7) NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS193 is TA14451A. HCTS193MS HCTS193MS Q1 P1 VCC (2) (1) (16) (8) (9) (10) ...

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