hcts32ms Intersil Corporation, hcts32ms Datasheet

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hcts32ms

Manufacturer Part Number
hcts32ms
Description
Radiation Hardened Quad 2-input Or Gate
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS32MS is a Radiation Hardened Quad 2-Input OR
Gate. A Low on all inputs forces the output to a Low state.
The HCTS32MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS32MS is supplied in a 14 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS32DMSR
HCTS32KMSR
HCTS32D/
Sample
HCTS32K/
Sample
HCTS32HMSR
(Typ)
- VIL = 0.8V Max
- VIH = VCC/2 Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
RAD (Si)/s 20ns Pulse
C
C
C
5 A @ VOL, VOH
|
Copyright
o
o
C
C
12
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
o
SCREENING
C to +125
©
RAD (Si)/s
LEVEL
Intersil Corporation 1999
o
-9
C
2
/mg
Errors/Bit-Day
14 Lead SBDIP
14 Lead
Ceramic
Flatpack
14 Lead SBDIP
14 Lead
Ceramic
Flatpack
Die
PACKAGE
450
Pinouts
Functional Diagram
NOTE: L = Logic Level Low, H = Logic level High
HCTS32MS
GND
(2, 5, 10, 13)
A1
B1
A2
B2
(1, 4, 9, 12)
Y1
Y2
Bn
An
An
H
H
L
L
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
MIL-STD-1835 CDFP3-F14
A1
B1
Y1
A2
B2
Y2
MIL-STD-1835 CDIP2-T14
1
2
3
4
5
6
7
TRUTH TABLE
Quad 2-Input OR Gate
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Bn
H
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
OUTPUTS
(3, 6, 8, 11)
Yn
H
H
H
L
Yn
518638
2248.2
VCC
B4
A4
Y4
B3
A3
Y3

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hcts32ms Summary of contents

Page 1

... Gate. A Low on all inputs forces the output to a Low state. The HCTS32MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS32MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART ...

Page 2

... VIL = 0.8V (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO 3. Force/Measure functions may be interchanged. Specifications HCTS32MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . ...

Page 3

... Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = VCC/2, VIL = 0.8V , IOL = 50 A Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = VCC/2, VIL = 0.8V, IOH = -50 A Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND Specifications HCTS32MS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 10, 11 +125 9 ...

Page 4

... Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A inspection in accordance with method 5005 of MIL-STD-883 may be exercised. Specifications HCTS32MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour TABLE 6 ...

Page 5

... Each pin except VCC and GND will have a resistor of 1k OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS32MS TABLE 7. TOTAL DOSE IRRADIATION TEST PRE RAD POST RAD ...

Page 6

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS32MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 7

... AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS32MS AC Load Circuit DUT TPHL CL = 50pF RL = 500 TTHL 80% 20% UNITS 456 TEST POINT CL RL 518638 Spec Number ...

Page 8

... Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 m x 100 mils Metallization Mask Layout B1 (2) Y1 (3) A2 (4) B2 (5) HCTS32MS HCTS32MS A1 VCC B4 (1) (14) (13) (6) (7) (8) Y2 GND Y3 457 (12) A4 (11) Y4 (10) B3 (9) A3 518638 Spec Number ...

Page 9

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HCTS32MS EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...

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