hcts7266ms Intersil Corporation, hcts7266ms Datasheet

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hcts7266ms

Manufacturer Part Number
hcts7266ms
Description
Radiation Hardened Quad 2-input Exclusive Nor Gate
Manufacturer
Intersil Corporation
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS7266MS is a Radiation Hardened quad 2-Input
exclusive NOR Gate. A logic level high on either one of the inputs
(A or B) will force the output (y) low. A high on both inputs, or a low
on both inputs will force the output to a logic high.
The HCTS7266MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family with TTL
input compatibility.
The HCTS7266MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS7266DMSR
HCTS7266KMSR
HCTS7266D/
Sample
HCTS7266K/
Sample
HCTS7266HMSR
(Typ)
- VIL = 0.8V Max
- VIH = 2.0V Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
C to +125
C to +125
RANGE
10
+25
+25
+25
RAD (Si)/s 20ns Pulse
o
o
o
5 A at VOL, VOH
C
C
C
o
o
C
C
12
o
C to +125
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
RAD (Si)/s
LEVEL
o
-9
C
2
/mg
Errors/Bit-Day
14 Lead
SBDIP
14 Lead
Ceramic
Flatpack
14 Lead
SBDIP
14 Lead
Ceramic
Flatpack
Die
PACKAGE
HCTS7266MS
1
Pinouts
Functional Diagram
NOTE: L = Logic Level Low, H = Logic level High
GND
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Quad 2-Input Exclusive NOR Gate
An
Bn
A1
B1
Y1
Y2
A2
B2
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14
A
H
H
L
L
(FLATPACK) MIL-STD-1835 CDFP3-F14
GND
INPUTS
A1
B1
A2
B2
Y1
Y2
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
B
H
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
B4
A4
Y4
Y3
B3
A3
OUTPUTS
H
H
Y
L
L
518627
3384.1
VCC
B4
A4
Y4
Y3
B3
A3
Yn

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hcts7266ms Summary of contents

Page 1

... The HCTS7266MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radia- tion hardened, high-speed, CMOS/SOS Logic Family with TTL input compatibility. The HCTS7266MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART ...

Page 2

... VIL = 0.80V (Note 3) NOTES: 1. All voltages referenced to device GND. 2. Force/Measure functions may be interchanged. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS7266MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . ...

Page 3

... VCC = 4.5V, VIH = 4.5V, VOUT = VCC-0.4V, VIL = 0V Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = VCC/2, VIL = 0.8V, IOL = 50 A Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = VCC/2, VIL = 0.8V, IOH = -50 A Specifications HCTS7266MS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 10, 11 +125 9 10, 11 +125 ...

Page 4

... Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A in accordance with method 5005 of MIL-STD-883 may be exercised. Specifications HCTS7266MS (NOTES 1, 2) CONDITIONS 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour TABLE 6 ...

Page 5

... Each pin except VCC and GND will have a resistor of 1K OPEN 3, 4, 10, 11 NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS7266MS TABLE 7. TOTAL DOSE IRRADIATION TEST PRE RAD POST RAD ...

Page 6

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS7266MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 7

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCTS7266MS AC Load Circuit TPHL ...

Page 8

... Metallization Mask Layout B1 (2) Y1 (3) Y2 (4) A2 (5) NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS7266 is TA14436A. HCTS7266MS HCTS7266MS A1 VCC B4 (1) (14) (13) (6) (7) ...

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