vp520s Mitel, vp520s Datasheet - Page 11

• Manufacturer Part Number: vp520s
• Description: Pal/ntsc To Cif/qcif Converter
• Manufacturer: Mitel

which are actually stored, but the coefficients are different for
the even and odd field generation. Thus a total of ten sets of
five coefficients are internally stored. In effect we have inter-
polated by five and then decimated by three in order to
produce the complete NTSC frame.
NTSC chrominance lines, and one filtered line in every six is
then ignored. This is mechanized by reading each CIF chromi-
nance line twice for every pair of luminance lines. The same
filtering and discard technique as used in the luminance
channel is then applied, using five sets of coefficients for each
field. Ten sets are thus needed to produce two NTSC fields.
We have effectively interpolated by ten and then decimated by
three to produce 480 chrominance lines for the complete
frame.
output buffering is not used. Instead a sequence is used which
will generate 10 NTSC lines in any field from six QCIF
luminance lines and three chrominance lines. Figure 9 illus-
trates how the first and fourth lines are used once and the
second, third, fifth, and sixth used twice to produce QCIF
luminance. Since this 1 - 2 - 2 sequence is used twice in every
ten lines, only five rather than ten sets of coefficients are
actually needed for each field ( ten sets in total ).
and the second line is used four times. Thus ten sets of
coefficients are needed for each field ( twenty sets in total ).
Each luminance and chrominance set consists of seven
coefficients, since six line delays are provided for the filters.
Five sets of coefficients are used to produce the five lines
Each CIF chrominance line is used to produce two filtered
When interpolating from QCIF to NTSC the additional
The first and third chrominance lines are used three times,
JTAG Test Interface
boundary scan loop of test registers placed between the pads
and the core of the chip. The control of this loop is fully JTAG/
IEEE 1149-1 1990 compatible. Please refer to this document
for a full description of the standard.
TCK and TRST. The TRST pin is an independent reset for the
interface controller and should be pulsed low, soon after
power up; if the JTAG interface is not to be used it can be tied
low permanently. The TDI pin is the input for shifting in serial
instruction and test data; TDO the output for test data. The
TCK pin is the independent clock for the test interface and
registers, and TMS the mode select signal.
all output transitions on TDO happen on its falling edge.
(no parity bit) and the following instructions are available.
separate INTEST instruction but allows EXTEST to drive the
internals of the device as well as to drive the output pins.
Output enables are thus present in the chain which are not
connected to pins but which allow EXTEST to be used to
control the impedance of all the outputs. The TOE pin, which
can separately be used to control the impedance of all the
outputs, can be monitored as an input through the scan chain
but cannot be used to control the outputs through the TAP
controller. The signals controlled by the various enables are
listed below:
The VP520S includes a test interface consisting of a
The interface has five dedicated pins: TMS, TDI, TDO,
TDI and TMS are clocked in on the rising edge of TCK, and
Instructions are clocked into the 3 bit instruction register
Instruction Register
( MSB first )
111
000
010
The TAP controller used in this device does not support a
PAD NAME
dram_oeb
refs_oeb
csync_oeb
cgtout_oeb
d_oeb
m_oeb
c_dec_b
yuv_oeb
cdata_oeb
SIGNALS CONTROLLED
A8:0, RAS, CAS, R/W
FREF, VREF, HREF
CLMP, CSYNC, HBLNK
D15:0
M7:0, MCLK, FSIG
CREF
Y7:0, C7:0
HD7:0
VREF, HREF, CSYNC and
CLMP)
Test function only
Name
BYPASS
EXTEST (Inversion except for
SAMPLE/PRELOAD
VP520S
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