rsc-464 ETC-unknow, rsc-464 Datasheet - Page 11

• Manufacturer Part Number: rsc-464
• Description: Speech Recognition Processor
• Manufacturer: ETC-unknow

Preliminary Data Sheet
RSC-464
The external memory interface (A[19:0], D[7:0], -RDR, -WRC, -RDF and –WRD) automatically goes into a high-Z
state and is pulled up by a 100 Kohm internal resistor when the “pdn” bit is set, to conserve current.
Register E8 contains both the “pdn” bit and the processor clock selector (Bit2). The clock selector bit determines
whether the 14.32 clock (“fast clock”) or the 32KHz clock (“slow clock”) will be used at wakeup time, independent of
what clock rate was being used before or during power down mode. This allows the processor clock after wakeup
to be the same or different from the processor clock used when the power-down flag was set. (see “Clock” section
for complete explanation)
To minimize power consumption, most operational blocks on the chip also have individual power controls that may
be selectively enabled or disabled by the programmer.
Wakeup from powerdown
Note that a Wakeup event does not cause a reset. The processor, which was "frozen" when register E8.Bit7 was
set, will be restarted without loss of context. A reset of the chip will also cancel a power down mode, but with a
corresponding loss of processor context.
Wakeup events terminate a power-down state. In Sleep mode, only an I/O Wakeup event can initiate a wake-up. In
Idle mode, an Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wakeup.
An I/O Wakeup is enabled by setting the bit(s) high in registers E9 corresponding to the desired I/O pin(s) to be
used for wakeup. E9 controls P0 wakeup enable. The polarity of the wakeup event is controlled by putting the
appropriate port pin in input mode and writing the appropriate bit in the output register for that pin to the desired
polarity. (see “General Purpose I/O” section for complete explanation) When the value on the wakeup pin equals
the value in the output register a wakeup will occur. When an I/O Wakeup occurs register FB.Bit1 will be set high.
The user should clear this bit once the status is noted, so that it can indicate future wakeup events.
A T2 Wakeup is enabled by setting register E8.Bit6 high. Then an overflow of timer T2 will generate an interrupt
request, which in turn will trigger a wakeup event. Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared
prior to powering down to allow the wakeup interrupt request to occur. (the “Timers/Counters” section describes
how timer T2 is configured)
An Audio Wakeup is generated by special circuitry that can detect several classes of sounds, even while in power-
down mode. When the class of sound selected by the programmer is detected by this circuitry a wakeup event will
occur. (see the “Audio Wakeup” section for more information)
To determine the source of wakeup during powerdown, it is necessary to query FE.Bit1 and FB.Bit1. If FE.Bit1 is
set, then the wakeup was caused by T2. If FB.Bit1 was set, it was caused by I/O. If a wakeup occurs and neither
of these bits is set, then by process of elimination the wakeup was caused by Audio Wakeup.
General Purpose I/O
The RSC-464 has 16 general-purpose I/O pins (P0.0-P0.7 and P2.0-P2.7). Each pin can be programmed as an
input with weak pull-up (~200k: equivalent device); input with strong pull-up (~10k: equivalent device); input
without pull-up, or as an output with sufficient drive to light an LED. (See “DC Characteristics” section for I/O
electrical characteristics.) This is accomplished by programming combinations of bits of configuration registers
assigned to the I/O pins.
NOTE: Port 1 on the RSC-4128 has been removed on the RSC-464 to reduce cost. If an application began
as an RSC-4128 design, it should be reviewed to ensure Port 1 is not being used.
Two control registers, A and B, are used to control the nature of inputs and outputs for each port. Registers E6
(“p0CtlA”) and E7 (“p0CtlB”), and DE (“p2CtlA”) and DF (“p2CtlB”), are the control registers A and B for ports P0
and P2, respectively. Each port pin’s I/O configuration may be controlled independently by the state of it’s
corresponding bits in these registers. Control registers A and B together determine the function of the port pins as
follows:
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P/N 80-0282-A
© 2005 Sensory Inc.