rsc-464 ETC-unknow, rsc-464 Datasheet - Page 16

• Manufacturer Part Number: rsc-464
• Description: Speech Recognition Processor
• Manufacturer: ETC-unknow

RSC-464
The resolution of T1 and T3 is 8 bits, but the range is 23 bits. The longest interval that can be timed by T1 or T3 is
2^15*256 clocks = 9.3 seconds.
The 4-bit prescaler for T1 is in the Clock Extensions Register, (register D6.Bits[3:0]). The 4-bit prescaler for T3 is in
the Timer3 Control Register (register D9.Bits[3:0]).
In addition to its timing capability, T3 can also be configured as a counter of external events. In this configuration it
uses either the rising or falling edge of a signal applied to I/O pin P0.1. The selected transition is internally
synchronized to CLK1. The maximum external count rate for T3 is 447KHz.
The Timer3 Control Register contains the counting/timing options for T3. The register is write-only. Bits[6:4] provide
configuration control.
16
Prescaler value
0000
0001
0010
0011
0100
0101
0110
0111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
Bit6
x
0
1
0
1
Bit5
0
0
0
1
1
0: disable T3 and prescaler from counting/timing
1: enable T3
cleared by reset.
0: use rising edge for external event counting
1: use falling edge for external event counting
cleared by reset
0: use internal T3CLK for source (timing)
1: use external events on pin P0.1 for source (counting)
cleared by reset
0: normal operation
1: T3 is gated by pin P0.1 according to Bit6
cleared by reset.
Encoded prescaler for T3. (See prescaler table above).
cleared by reset.
Divisor
1
2
4
8
16
32
64
128
use LOW state on pin P0.1 for timer gating
use HIGH state on pin P0.1 for timer gating
Bit4
0
1
1
x
x
timer
source
T3CLK
T3CLK
T3CLK
P0.1
P0.1
Prescaler value
1000
1001
1010
1011
1100
1101
1110
1111
Configuration
timer
timer gated by P0.1 LOW
timer gated by P0.1 HIGH
count
edge
count P0.1 events, falling
edge
P/N 80-0282-A
P0.1
events,
rising
Divisor
256
512
1024
2048
4096
8192
16384
32768
Preliminary Data Sheet
© 2005 Sensory Inc.