gvt71128b18 ETC-unknow, gvt71128b18 Datasheet - Page 4

• Manufacturer Part Number: gvt71128b18
• Description: 128k Synchronous Burst Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS (continued)
BURST ADDRESS TABLE (MODE = NC/VCC)
BURST ADDRESS TABLE (MODE = GND)
March 4, 1998
Rev. 3/98
72, 73, 8, 9, 12, 13, 18,
1-3, 6, 7, 14, 16, 25,
28-30, 38, 39, 42, 43,
51-50, 53, 56, 57, 66,
75, 78, 79, 80, 95, 96
58, 59, 62, 63, 68, 69,
5, 10, 21, 26, 55, 60,
GALVANTECH
4, 11, 20, 27, 54, 61,
First Address
First Address
17, 40, 67, 90
15, 41,65, 91
QFP PINS
(external)
(external)
19, 22, 23
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A11
74, 24
70, 77
71, 76
97
86
83
84
85
31
64
DQ1-DQ16
SYMBOL
Second Address
Second Address
ADSP#
ADSC#
MODE
DQP1,
VCCQ
VSSQ
DQP2
ADV#
OE#
VCC
VSS
CE2
NC
ZZ
(internal)
(internal)
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground Output Buffer Ground: GND
I/O Supply Output Buffer Supply: +2.375 to 3.6V
Asynchro-
Ground
Output
Output
Supply
TYPE
Input-
Input-
Input-
Input-
Input-
input-
Static
Input/
Input/
Input
nous
-
, INC.
Chip enable: This active HIGH input is used to enable the device.
Output Enable: This active LOW asynchronous input enables the data
output drivers.
Address Advance: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address
advance).
Address Status Processor: This active LOW input, along with CE# being
LOW, causes a new external address to be registered and a READ cycle
is initiated using the new address.
Address Status Controller: This active LOW input causes device to be de-
selected or selected along with new external address to be registered. A
READ or WRITE cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects
LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED
BURST.
Snooze: This active HIGH input puts the device in low power consumption
standby mode. For normal operation, this input has to be either LOW or
NC (No Connect).
Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-DQ16.
Input data must meet setup and hold times around the rising edge of CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity
bit for DQ9-DQ16.
Power Supply: +3.3V -5% and +10%
Ground: GND.
No Connect: These signals are not internally connected.
Third Address
Third Address
(internal)
(internal)
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
128K X 18 SYNCHRONOUS BURST SRAM
4
Fourth Address
Fourth Address
(internal)
(internal)
DESCRIPTION
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A11
Galvantech, Inc. reserves the right to change products or specifications without notice.
GVT71128B18
PRELIMINARY