gvt71128b18 ETC-unknow, gvt71128b18 Datasheet - Page 5

• Manufacturer Part Number: gvt71128b18
• Description: 128k Synchronous Burst Sram
• Manufacturer: ETC-unknow

TRUTH TABLE
Note:
PARTIAL TRUTH TABLE FOR READ/WRITE
March 4, 1998
Rev. 3/98
OPERATION
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
READ
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
FUNCTION
GALVANTECH
1.
2. WEL# enables write to DQ1-DQ8 and DQP1. WEH# enables write to DQ9-DQ16 and DQP2.
3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4.
5. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be
X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + WEL#*WEH#]*GW# equals
LOW. WRITE# = H means [BWE# + WEL#*WEH#]*GW# equals HIGH.
Suspending burst generates wait cycle.
for OE# and staying HIGH throughout the input data hold time.
performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for
clarification.
GW#
H
H
H
H
L
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
USED
Next
Next
Next
Next
Next
Next
BWE#
, INC.
H
X
L
L
L
CE#
H
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
WEH#
CE2#
X
H
X
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
128K X 18 SYNCHRONOUS BURST SRAM
CE2
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
WEL#
5
X
H
H
X
L
ADSP# ADSC#
X
H
H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
L
L
L
ADV#
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
Galvantech, Inc. reserves the right to change products or specifications without notice.
WRITE#
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
OE#
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
GVT71128B18
PRELIMINARY
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D