DESCRIPTION
FEATURES
APPLICATION
BLOCK DIAGRAM
The M52757FP is a semiconductor integrated circuit for
the RGB interface. The device features switching signals
input from two types of image sources and outputting the
signals to the CRT display,etc. The frequency band of
video signals is 250MHz, acquiring high-resolution
images, and are optimum as an interface IC with high-
resolution CRT display and various new media.
It includes Sync-separator, Video-signal-detector, and
Sync-on G detector (SOG-DET.).
• Frequency band width : R.G.B ...................250MHz
• Input level : R.G.B...............................0.7Vp-p (Typ.)
• Video signal-detector
• Only the G channel is proveded with buffer video output.
• It is possible to save the consumption current by
• Include Sync Separation,Video signal detector, and
Sync-on G detector.
Responsive frequency............................... ~50MHz
Input level............................................0.7Vpp (Typ.)
Detected level......................................150mV (Typ.)
stopping current supply to Pin 2,4,6,20,24,30,33,35
because SOG-DET can be operated with only Vcc5
(Pin 15) as power save mode.
Display monitor
INPUT1(R)
Vcc2(R)
36
1
OUTPUT(R)
Vcc1(R)
35
2
INPUT1(G)
R
34
3
(Measure bottom to DET.level)
Vcc1(G)
Vcc2(G)
33
4
INPUT1(B)
OUTPUT(G)
32
5
G
Vcc1(B)
31
6
INPUT2(R)
Vcc2(B)
30
7
OUTPUT(B)
29
8
B
INPUT2(G)
28
9
(for Sync on G)
G Buffer out
10
27
PIN CONFIGURATION (TOP VIEW)
G
RECOMMENDED OPERATING CONDITION
INPUT2(B)
Sync SEP in
Sync
11
26
sepa
VideoDET-Hold
Suply voltage range
Rated voltage
Sync SEP out
SyncDET1
12
25
SyncDET1
SyncDET2
Input1 (G)
Input1 (R)
Input2 (R)
Input1 (B)
Input2 (B)
S-DETout
V-DETout
Input2(G)
Vcc1 (R)
Vcc1 (G)
SWITCH
Vcc1 (B)
GND1
GND5
SyncDET2
Vcc3
24
13
Vcc5
MITSUBISHI ICs (Monitor)
V-DET in 3
WIDE BAND ANALOG SWITCH
S-DET
14
23
OUT
15
16
17
18
10
11
12
13
14
1
2
3
4
5
6
7
8
9
POWER
Vcc(5V)
Vcc5
22
15
SAVE
VideoDET-Hold
M52757FP
V-DET in 2
16
5.0V
21
4.75~5.5V
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
V-DET out
OR
Vcc4
20
17
VCC2 (R)
OUTPUT (R)
GND2(R)
Vcc2(G)
OUTPUT(G)
GND2 (G)
Vcc2 (B)
OUTPUT(B)
CND2(B)
G Buffer out
Sync SEP in
Sync SEP out
Vcc3
V-DET in3
GND4
V-DET in2
Vcc4
V-DET in1
Outline: 36P2R-D
V-DET in 1
18
19
(
1
SW GND : INPUT1
SW OPEN : INPUT2
/ 5 )