tmpr3927f TOSHIBA Semiconductor CORPORATION, tmpr3927f Datasheet
tmpr3927f
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tmpr3927f Summary of contents
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... GENERAL DESCRIPTION The TMPR3927F (to be called “TX3927” hereinafter standard micro controller of the 32-bit RISC Microprocessor TX39 family. The TX3927 uses the TX39/H2 processor core as the CPU. The TX39/H2 processor core is a RISC CPU core Toshiba developed based on the R3000A architecture of MIPS Technologies, Inc ...
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... Direct Memory Access Controller (DMAC) q Independent 4-channel DMA Supports 8/16/32-bit wide I/O devices Supports Internal/External transfer requests Supports both Dual Address and Single Address transfer modes Support of word aligned memory to memory transfers using 4-word/8-word burst reads and writes TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 2/22 ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 3/22 ...
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... SYSTEM CONFIGURATION 3.1 TMPR3927F Block Diagram 3.2 SYSCLK A[19:2]/(Boot Signals) D[31:0]/(Boot Signals) ACK* BUSERR* RESET* NMI* TEST* SCAN_ENB* CLKEN PIO[15:0] TIMOUT[1] TIMIN[1] TIMOUT2 TIMIN2 *Note: This diagram shows the full set of functional signal connections. Due to pin multiplexing, not all of these signals will be available. ...
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... GNT[ GNT[ REQ[ REQ[ REQ[ REQ[ PCIAD[31 PCIAD[30 VSS2 89 60 VDDS 90 TMPR3927F TENTATIVE Signal Pin No. Signal VSS 91 VSS2 PCIAD[29] 92 DEVSEL* PCIAD[28] 93 STOP* PCIAD[27] 94 PERR* VSS 95 SERR* PCIAD[26] 96 PAR PCIAD[25] 97 C_BE[1] PCIAD[24] 98 VSS VSS ...
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... ADDR[13] 204 175 ADDR[14] 205 176 VSS 206 177 ADDR[15] 207 178 ADDR[16] 208 179 ADDR[17] 209 180 VDDS 210 TMPR3927F TENTATIVE Signal Pin No. Signal VSS2 211 VSS2 XIN 212 SDCS*[0] XOUT 213 SDCS*[1] VDD2 214 SDCS_CE*[2] VDD2 215 SDCS_CE*[3] PLLVDD ...
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... Asserted high if an external clock source is selected, or attached to an external crystal with a frequency of 1/16 of the core frequency. CLKEN I Clock Enable Enables internal clock generator. Should be asserted via external logic when V reaches minimum specification and XIN has started and is stable. Signal is connected to internal pull-up resistor. TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 7/22 dd ...
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... SDRAMs. During a read cycle, the DQM functions as the control of the SDRAM output buffers. The DQMs also function as byte write enables to DIMM Flash during a write cycle. WE* O Write Enable Write enable signal for access of synchronous memory devices. CKE O Clock Enable Used for synchronous memory devices. TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 8/22 ...
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... Indicates beginning and duration of an transaction. TRDY* I/O Target ready IRDY* I/O Initiator ready STOP* I/O STOP* indicates that the current Target is requesting Initiator to stop the current transaction. DEVSEL* I/O Device select Indicates that an active device has decoded its address as the target of the current access. TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 9/22 ...
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... PIO/TIMER and SDCS_CE[7] functions. Signal is connected to internal pull-up resistor. O DMA Acknowledge DMAACK[3:0] DMA acknowledge to external devices. Signals are software assigned and shared with PIO/TIMER and SDCS_CE[6] functions. Signal is connected to internal pull-up resistor. I/O DMADONE* DMA Transfer/Chain Finished Signal is connected to internal pull-up resistor. TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 10/22 ...
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... During serial monitor bus operation, this clock is half the frequency of the TX39/H2 core operating clock. GSDAO[1:0] O Serial Data and Address Output/Target PC These signals function as serial data/address outputs when operating with the serial monitor bus interface or as debug interrupt input when operating with the PC trace interface. TMPR3927F TENTATIVE TAEC_rev4_11-Jan-2000 11/22 ...
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... Power pins and Total pin count PLL_VSS, I Power and Ground pins to internal PLL circuit. PLL_VDD VDD2 I Power pins at 2.5V VDDS I Power pins at 3.3V VSS2,VSS I Ground pins Pins: 240 pins Total Pin Count This signal must be low when a real-time debugging system is TAEC_rev4_11-Jan-2000 12/22 TMPR3927F TENTATIVE ...
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... DC Characteristics Symbol V DDS V DD2 V IN1 REQ[3:0], V IN2 T STG P D Symbol Condition I/O V DDS V DD2 T c TMPR3927F TENTATIVE Rating Unit V -0.3 4.5 -0.3 ~ 3.6 V -0.3 6.7V V -0.3 V DDS + 0.3V -40 125 C 2 Max. 3.0 3 ...
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... RXD[1:0], CTS[1:0] V IL2 V IH1 RXD[1:0], CTS[1:0] RXD[1:0], CTS[1:0] V IH2 I OL1 ( 0.4V I OL2 ( 0.4V ( 2.4V ( 2.4V (3) f=133MHz, V DDS = 3.6V (3) f=133MHz, V DDS = 2. RST TMPR3927F TENTATIVE = DDS = 3.3V 0.3V, V DD2 = 2.5V 0.2V 0V Max. Unit V DD 0.2 0.8 V DDS 0.8 V DDS 0.3 2.0 5 ...
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... Output Low Vol t age Input leakage current ( DDS = 3.3V 0.3V, V DD2 = 2.5V 0.2V 0V) c Symbol Condition V IL3 V IH3 OUT = -2mA OUT = 3mA, 6mA < < TMPR3927F TENTATIVE Max. Unit -0.5 V DDS x 0 DDS x 0.5 5 DDS x 0 DDS x 0.1 V -10 ...
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... IN 6.25~8.33 R OUT 10 C IN, C OUT ( Symbol Recommended Val 66. DDS = 3.3V 0.3V, V DD2 = 2.5V 0.2V 0V) c Symbol Condition MIN. t STA f=6.25 8.75MHz Filter0 Filter1 TMPR3927F TENTATIVE Unit MHz Unit MHz TYP Unit - TAEC_rev4_11-Jan-2000 16/22 ...
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... Symbol Symbol External Capacitor C Filter Recommended Val u e Unit 1800 (using 16x divider) pF 220 (using 2x divider) pF TAEC_rev4_11-Jan-2000 17/22 TMPR3927F TENTATIVE ...
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... Cycle Time (Half-speed bus mode h/Low Level Min Half-Speed High/Low Level Output Delay Output Hold Input Setup Input Hold Data Active to Hi-Z Data Hi-Z to Active ( DDS = 3.3V 0.3V, V DD2 = 2.5V 0.2V 0V 50pF for SDCLK[4:0]) c Description TMPR3927F TENTATIVE Min Max Unit ...
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... V > 2.2 95 out 2.2 > V > 0. 0.023 out out 0.71>V > V out 0.71 out -5 <V < -1 -25+(Vin+1)/ 0.015 in 0.4V to 2.4V load 1 2.4V to 0.4V load 1 TAEC_rev4_11-Jan-2000 19/22 TMPR3927F TENTATIVE 0.25V 0V 50pF Max. Unit V/ ...
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... Definition of AC characteristics (of PCI pins) PCICLK Output Delay Tri-state Output Delete PCICLK. Input tsym, tsysh tsysm, tsysmh toh tdaz tsu tih ton tval tcyc tcyc toff 0.4Vdd 0.4Vdd 0.4Vdd tsu 0.4Vdd TMPR3927F TENTATIVE tdza tHigh tHigh tLow tLow 0.4Vdd th Valid 0.4Vdd TAEC_rev4_11-Jan-2000 20/22 ...
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... PACKAGE DIMENSION QFP240-P-3232-0.5 TMPR3927F TENTATIVE Unit: mm TAEC_rev4_11-Jan-2000 21/22 ...
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... QFP240-P-3232-0.5 TMPR3927F TENTATIVE Unit: mm TAEC_rev4_11-Jan-2000 22/22 ...