tmpr3907af TOSHIBA Semiconductor CORPORATION, tmpr3907af Datasheet
tmpr3907af
Related parts for tmpr3907af
tmpr3907af Summary of contents
Page 1
TX System RISC 1. GENERAL DESCRIPTION The TMPR3907F (TX3907 TX39 family microprocessor incorporating a 32-bit TX39/H core developed by Toshiba. Designed for use in OA equipment, the TX3907 also incorporates such peripheral circuits as a memory controller, ...
Page 2
SYSTEM CONFIGURATION 3.1 TX3907 BLOCK DIAGRAM XIN XOUT PLLOFF* SYSCLK PCIAD[31:0] CBE[3:0] PAR FRAME* TRDY* IRDY* PCIC STOP* DEVSEL* REQ[2:0]* GNT[2:0]* PCICLK PERR* SERR* IDSEL TX39/H core I-Cache TX39 D-Cache WBU APU DSU G-Bus I/F DRAMC PLL (3ch.) CG ...
Page 3
PIN DESCRIPTION 4.1 PIN ASSIGNMENT Pin No. Signal Name Pin No. 1 INT[ INT[ GNT[2 GNT[1 GNT[0 ROMA[23 ROMA[22 CE[4]*/SCS[1 VDD 39 10 ...
Page 4
Pin No. Signal Name Pin No. Signal Name 121 D[11] 143 122 D[4] 144 123 D[12] 145 124 D[13] 146 125 D[5] 147 126 D[14] 148 127 D[6] 149 128 D[15] 150 129 D[7] 151 130 VSS 152 131 VSS ...
Page 5
PIN FUNCTIONS Signal Name I/O System interface signals SYSCLK O System clock Outputs the same clock as that of the TX39/H core (Full-Speed Bus mode) or half the clock of the TX39/H core (Half-Speed Bus mode). Output can be ...
Page 6
Clock signals XIN I Crystal input Connect a crystal oscillator to this pin. The TX39/H core operates at eight times the crystal oscillator. XOUT O Crystal output Connect a crystal oscillator to this pin. PLLOFF* I PLL off Used to ...
Page 7
PCI interface signals PCIAD[31:0] I/O PCI address and data Address and data multiplex bus. CBE[3:0]* I/O Bus command and byte enable Command and byte enable signal. PAR I/O Parity Parity signal for PCIAD[31:0] and CBE[3:0]. FRAME* I/O Cycle frame Indicates ...
Page 8
Debugging interface Four of the eight debugging interface pins are also used as SIO pins. When ROMA[16:12] is set to 11111 on the RESET* signal rising edge, these pins are used for an external real-time debug system. When ROMA[16:12] is ...
Page 9
TX3907 initial setting signals These initial setting input signals use same pins as those for ROMA signals. The signals are loaded to the TX3907 on the RESET* signal rising edge and are used for the TX3907 initial settings. The signals ...
Page 10
PCI3 ROMA[11] PCI clock divisor Sets the PCI clock frequency valid when PCICLKIN* is High. High: Low: CGRESET* ROMA[10] CGRESET Resets the built-in clock generator. While the RESET* signal is low, functions as the CGRESET* signal. D0BASE ROMA[9] ...
Page 11
ELECTRICAL CHARACTERISTICS 5.1 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage D[31:0], DRESET*/CTS*, SDI/SIN Other than above Storage Temperature Maximum Power Dissipation Note: Exceeding the absolute maximum ratings when using this LSI may permanently damage the device. In normal ...
Page 12
DC CHARACTERISTICS 5.3.1 DC Characteristics of Pins Other Than PCI Interface Pins Parameter Symbol Low-level input voltage V V High-level input voltage V IH1 V IH2 Low-level output current I OL1 I OL2 High-level output current I OH1 I ...
Page 13
DC Characteristics of PCI Interface pins Parameter Symbol Low-level input voltage V ILP High-level input voltage V IHP Low-level output voltage V OL High-level output voltage V OH Input leakage current _= ...
Page 14
CRYSTAL OSILLATOR CHARACTERISTICS 5.4.1 Recommended Oscillator Conditions Parameter Crystal oscillator Frequency Output resistance External Capacitor Crystal oscillator Rising time Falling time (1) Reference values. Refer to the latest data provided by the manufacturer of the crystal oscillator. 5.4.2 Electrical ...
Page 15
AC CHARACTERISTICS (OTHER THAN PCI INTERFACE PINS) 5.5.1 Table of AC Characteristics (Unless otherwise specified, T Parameter Symbol t SYSCLK Full speed bus mode sys t SYSCLK Half speed bus mode sysh t ROMA[23:2] Output delay 1 t SPA[1:0] ...
Page 16
Definition of AC Characteristics In Full-Speed Bus mode, all signals operate on the SYSCLK rising edge. In Half-Speed Bus mode, only the SCS access signals operate on the SYSCLK rising edge. Other access signals operate on the SYSCLK rising ...
Page 17
Timing Diagram ROM read (Full-Speed Bus mode, single read, 2 waits) SYSCLK t 1 ROMA[23: SPA[1: CASBE[3:0 LAST*/RD* WR* ACK CE[n]* OE* SWE LEAFA*, LEAFB* D[31:0] 2 waits ...
Page 18
ROM read (Full-Speed Bus mode, page ROM, burst read, 1-0 waits) TMPR3907F TENTATIVE 1998-07-01 18/29 ...
Page 19
ROM read (Full-Speed Bus mode, page ROM, burst read, interleave, 1-0 waits) TMPR3907F TENTATIVE 1998-07-01 19/29 ...
Page 20
SRAM write (Full-Speed Bus mode, single write, 2 waits) SYSCLK t 1 ROMA[23: SPA[1: CASBE[3:0 LAST*/RD WR* ACK CE[n]* OE* SWE LEAFA*, LEAFB* D[31:0] 2 waits VALID ...
Page 21
DRAM read (Full-Speed Bus mode, single read, 1 wait) SYSCLK t 12 DRAM[12:0] RAS[n]* CASBE[3:0 LAST*/RD* WR* ACK* WE* D[31:0] 1 wait t 12 ROW COLUMN TMPR3907F TENTATIVE t 3 VALID F t ...
Page 22
DRAM read (Full-Speed Bus mode, EDO burst, 0-0 wait) TMPR3907F TENTATIVE 1998-07-01 22/29 ...
Page 23
DRAM write (Full-Speed Bus mode, single write, 1 wait) SYSCLK t 12 DRAMA[12:0] RASm[n]* CASBE[3:0 LAST*/RD WR* ACK WE* D[31:0] 1 wait t 12 ROW COLUMN VALID ...
Page 24
DRAM write (Full-Speed Bus mode, EDO burst, 0-0 wait) TMPR3907F TENTATIVE 1998-07-01 24/29 ...
Page 25
SCS read (Half-Speed Bus Mode, single read, external ACK*) SYSCLK t 1 ROMA[23: SPA[1: CASBE[3:0 LAST*/RD* WR* ACK SCS[n]* LEAFA*, LEAFB* D[31: VALID t 2 VALID t 3 VALID t ...
Page 26
SCS write (Half-Speed Bus Mode, single write, external ACK*) SYSCLK t 1 ROMA[23: SPA[1: CASBE[3:0]* LAST*/RD WR* ACK SCS[n]* LEAFA*, LEAFB D[31:0] INVALID VALID VALID VALID ...
Page 27
Interrupt SYSCLK t 47 INT[n] NMI* SYSCLK t 45 NMI* Power-on reset V DD PLLOFF* SYSCLK t STA ROMA[10] (CGRESET*) RESET* TMPR3907F TENTATIVE 1998-07-01 27/29 ...
Page 28
AC CHARACTERISTICS (PCI INTERFACE PIN) 5.6.1 AC Characteristics Table (Unless otherwise specified, T Parameter t PCICLK cycle time pcyc t Valid output delay from PCICLK (bus connection) val t (ptp) Valid output delay from PCICLK (p-p connection) val t ...
Page 29
PACKAGE DIMENSIONS QFP208-P-2828-0.50 TMPR3907F TENTATIVE Unit mm 1998-07-01 29/29 ...
Page 30
TMPR3907F TENTATIVE 1998-07-01 30/29 ...