tmpr3922au TOSHIBA Semiconductor CORPORATION, tmpr3922au Datasheet
tmpr3922au
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tmpr3922au Summary of contents
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... GENERAL DESCRIPTION The TMPR3922AU is a single-chip integrated digital ASSP for PDA(Personal Digital Assistants). The TMPR3922AU consists of PDA system support logic, integrated with the TX3920 processor Core designed by Toshiba. 2. FEATURES - R3000A-based TX3920 Processor Core RISC architecture developed by The MIPS Group, a division of Silicon Graphics, Inc. ...
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... Touchscreen (Resistive) Phone Jack 1-2 PCMCIA Slots 32kHz 32-bit Bus ID ROM Thermistor FIR High speed serial port 3.3V DAA or RF Xceiver FIG. 3.1 SYSTEM BLOCK DIAGRAM TMPR3922AU LCDC LCD 1-64 MBytes ROM 1-32 MBytes(s) DRAM AC Power Supply Adapter Main Backup (Lithium) T TC35143F (Analog Device) 64-pin QFP ...
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... SYSCLK Clock Module 6MHz System Interface Module (SIM) Data CPU Core Addr TLB System Interface Unit (SIU) Module Arbitration/DMA/Addr Decode Data Addr FIG. 3.2 TMPR3922AU BLOCK DIAGRAM TMPR3922AU Data to Memory Addr Control to high CHI Module speed serial to IR IrDA Module UART Module ...
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... D [15:8] becomes D [7:0] becomes CAS3* becomes CAS2* becomes CAS1* becomes CAS0* becomes <Note> The connection between the TMPR3922AU and Memory depends on the endianess. 3.3.1 MEMORY CONNECTIONS (Big Endian) TMPR3922AU D[31] 133 D[31] D[24] 145 D[24] D[23] 146 D[23] D[16] 159 D[16] D[15] 27 D[15] D[8] D[7] D[0] CAS3* 195 CAS3* CAS2* 197 CAS2* CAS1* 198 CAS1* CAS0* 199 CAS0* ...
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... CAS1* 197 CAS1* CAS0* 195 CAS0* RAS0* 194 RAS0* WE* A[12:0] Pin No. CAS1* CASHI* CAS0* CASLO* 2 D[24] RAS0* RAS* WE* WE* A[12:0] ADDR CAS3* CAS HI* CAS2* CAS MH* CAS1* CAS ML* CAS0* CAS LO* RAS0* RAS* WE* WE* 169 WE* A[12:0] ADDR A[12:0] Little Endian TMPR3922AU BANK0 16bit DRAM DATA D[15:0] BANK1 32bit DATA D[31:0] 2-FEB-1999 / 5 45 ...
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... TESTCPU 72 I TESTIN 73 O BCLK 74 I TESTAIU 75 VSS 76 I VCC3 77 O BC32K 78 VDDL 79 I C32KlN 80 O C32KOUT ( ) indicates the signal name in the Little endian mode TMPR3922AU NO. I/O SIGNAL NAME 81 VSS 82 O PWRCS 83 I PWRlNT 84 I PWROK 85 I/O IO[ ONBUTN 87 I PON CPURES* ...
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... O CAS3* (CAS0*) 196 VDDH – 197 O CAS2* (CAS1*) 198 O CAS1* (CAS2*) 199 O CAS0* (CAS3*) 200 VSS – indicates the signal name in the Little endian mode TMPR3922AU NO. I/O SIGNAL NAME 201 VDDL – 202 O DCKE 203 – VSS 204 I DCLKIN 205 O DCLKOUT 206 – ...
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... ALE signal. For static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from the TMPR3922AU's address bus) are held afterward by the TMPR3922AU for the remainder of the address bus cycle. ALE ...
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... This pin is the card wait signal from PCMCIA card slot 2. CARD1WAIT* I This pin is the card wait signal from PCMCIA card slot 1. MCS1WAIT* I This pin is the wait signal from the external device 1. MCS0WAIT* I This pin is the wait signal from the external device 0. *Active-low signal TMPR3922AU DESCRIPTION 2-FEB-1999 / 9 45 ...
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... This pin is used to request external arbitration. If the TESTAIU signal is high and the TESTAIU function has been enabled, then once DGRNT* is asserted, external logic can initiate reads or writes to the TMPR3922AU registers by driving the appropriate input signals. If the TESTAIU signal is low or the TESTAIU function has not been enabled, then the TMPR3922AU memory transactions are halted and certain memory signals will be tri-stated when DGRNT* is asserted in order to allow an external master to access memory ...
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... I/O This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes output, this pin allows the TMPR3922AU to be the master CHI sync source input, this pin allows an external peripheral to be the master CHI sync source and the TMPR3922AU CHI module will slave to this external sync ...
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... This signal provides power for the DRAM and/or SDRAM. This supply must be off when VSTANDBY is first asserted, and remain off until the system is powered up by the assertion of PWRCS. When the software subsequently powers down the system it may choose to keep this supply on to preserve the contents of memory. TMPR3922AU DESCRIPTION 2-FEB-1999 / ...
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... First, SIBMCLK can be configured as a high-rate output master clock source required by certain external codec devices. ln this mode all SIB clocks are synchronously slaved to the main TMPR3922AU system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock source. In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source, which is asynchronous with respect to CLK2X ...
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... IR analog circuitry. CARDET I This pin is the UART receive signal to the UARTB module or is the carrier detect input signal from the external communication IR analog circuitry if Consumer IR module is enabled. FIROUT O This pin is the FIR/SIR transmit signal from the IRDA(FIR/SIR) module. TMPR3922AU DESCRIPTION 2-FEB-1999 / 14 45 ...
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... Endian Pins NAME I/O ENDIAN I This pin is used to select the endian state of the TMPR3922AU. The "1" level input sets the endian state to the big endian, while the "0" level input to the little endian. Test Pins NAME I/O TESTAIU I This pin is used to define if the Boot ROM bits wide. If the TESTAIU pin is asserted during reset, the BIU will assume a 32-bit Boot ROM ...
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... PIN USAGE INFORMATION This section contains tables summarizing various aspects of the pin usage for the TMPR3922AU. TABLE 4.3a lists the standard versus multi-function usage for each TMPR3922AU pin, if applicable. Those signal names shown in parentheses are test signals for debugging purposes only. The column ...
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... Standard Function TMPR3922AU pin (I = input output) PWROK PWROK (I) ONBUTN ONBUTN (I) CPURES* CPURES* (I) PON* PON* (I) TXD TXD (O) RXD RXD (I) CS0* CS0* (O) CS1* CS1* (O) CS2* CS2* (O) CS3* CS3* (O) MCS0* MCS0* (O) MCS1* MCS1* (O) MCS0WAIT* MCS0WAIT* (I) MCS1WAIT* MCS1WAIT* (I) CHIFS CHIFS (I/O) CHICLK CHICLK (I/O) CHIDOUT CHIDOUT (O) CHIDIN ...
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... TMPR3922AU pin (I = input output) SIBSYNC SIBSYNC (O) SIBDOUT SIBDOUT (O) SIBDIN SIBDIN (I) SIBMCLK SIBMCLK (I/O) SIBSCLK SIBSCLK (O) SIBIRQ SIBIRQ (I) RXPWR RXPWR (O) CARDET CARDET (I) IROUT IROUT (O) IRINA IRINA (I) IRINB IRINB (I) FIROUT FIROUT (O) TESTAIU TESTAIU (I) TESTCPU TESTCPU (I) TESTIN TESTIN (I) CARDREG* CARDREG*(O) CARDIOWR* CARDIOWR* (O) CARDIORD* ...
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... The "PON* state" column defines the state of each pin at power-on reset (PON*). This condition is defined as initial power up of the TMPR3922AU, whereby the TMPR3922AU is initialized and the TMPR3922AU pins are reset to the state shown in the table. This state is entered after power is applied for the very first time (VSTANDBY is turned on but VCC3 is still turned off). ...
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... TABLE 4.3b TMPR3922AU POWER-DOWN PIN USAGE Power-Down Control TMPR3922AU pin powerdown = (vccon & vcc3)* D[31:0] MEMPOWERDOWN A[12:0] MEMPOWERDOWN ALE RD* WE* MEMPOWERDOWN CAS0* (WE0*) MEMPOWERDOWN CAS1* (WE1*) MEMPOWERDOWN CAS2* (WE2*) MEMPOWERDOWN CAS3* (WE3*) MEMPOWERDOWN RAS0* MEMPOWERDOWN RAS1* (DCS1*) MEMPOWERDOWN DCS0* MEMPOWERDOWN DCKE MEMPOWERDOWN DCLKIN DCLKOUT ...
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... Power-Down Control TMPR3922AU pin powerdown = (vccon & vcc3)* PWRCS PWRINT PWROK ONBUTN CPURES* PON* TXD POWERDOWN & MIOPD[24] (0) RXD POWERDOWN & MIOPD[23] (1) CS0* CS1* POWERDOWN & MIOPD[22] (1) CS2* POWERDOWN & MIOPD[21] (1) CS3* POWERDOWN & MIOPD[20] (1) MCS0* POWERDOWN & MIOPD[19] (0) MCS1* POWERDOWN & MIOPD[18] (0) MCS0WAIT* POWERDOWN & ...
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... Power-Down Control TMPR3922AU pin powerdown = (vccon & vcc3)* SIBSYNC SIBDOUT SIBDIN SIBMCLK POWERDOWN & MIOPD[12] (1) SIBSCLK SIBIRQ RXPWR POWERDOWN & MIOPD[17] (0) IROUT POWERDOWN & MIOPD[16] (0) CARDET IRINA IRINB FIROUT TESTAIU TESTCPU TESTIN CARDREG* POWERDOWN & MIOPD[11] (1) CARDIOWR* POWERDOWN & MIOPD[10] (1) CARDIORD* POWERDOWN & ...
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... FUNCTION SPECIFICATIONS 5.1 OUTLINE The TMPR3922AU consists of PDA system support logic, integrated with the TX3920 Processor Core designed by Toshiba. For details of the system support logic and the TX3920 processor Core, refer to the TMPR3922AU User's manual and TX39 family user's manual, respectively. 5.2 TX3920 PROCESSOR CORE The TX3920 processor core is a Toshiba-developed microprocessor core based on the R3000A RISC architecture developed by The MIPS Group, a division of Silicon Graphics, Inc ...
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... Random register TLB Random index. Page Mask register Hold a comparison mask that sets the variable page sige for each TLB entry. Wired register TLB Wired boundary. Debug register Control software debug exception. DEPC Program counter for software debug exception. TMPR3922AU 2-FEB-1999 / 24 45 ...
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... The TX3920 Processor Core has a high-speed multiplier/accumulator and supports 32-bit multiplier operations, with 64-bit accumulator in one cycle. 5.3 PERIPHERAL FUNCTIONS 5.3.1 CLOCK GENERATOR The TMPR3922AU uses an internal PLL and an external crystal oscillator to generate a clock with 16 times the input clock frequency. dissipation. 5.3.2 WRITE BUFFER The TMPR3922AU incorporates a four-stage write buffer ...
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... CLOCK MODULE The TMPR3922AU has a Clock module with the following features. The TMPR3922AU supports system-wide single crystal configuration, besides the 32 kHz RTC X’tal (reduces cost, power, and board space) common crystal rate divided to generate clock for CPU, sound, telecom, UARTs, etc. ...
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... IO pins and the 32 bi-directional multi-function IO pins each IO port can generate a separate positive and negative edge interrupt independently configurable IO ports allow the TMPR3922AU to support a flexible and wide range of system applications and configurations TMPR3922AU ...
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... IR MODULE The TMPR3922AU has an IR module with the following features. IR consumer mode allows control of consumer electronic devices such as stereos, TVs, VCRs, etc. programmable pulse parameters external analog LED circuitry IRDA communication mode IrDA 1.0 mode with filter is supported(BOF and EOF are detected by hardware and the bit pattern which data translation is necessay is detected and translated by hardware ...
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... RUNNING, DOZING and SLEEP 5.3.11 SERIAL INTERCONNECT BUS (SIB) MODULE The TMPR3922AU has a SIB module with the following features. The TMPR3922AU contains holding and shift registers to support the serial interface to the TC35143F codec devices interface compatible with slave mode 3 of the Crystal CS4216 codec synchronous, frame-based protocol The TMPR3922AU always master source of clock and frame frequency and phase ...
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... TIMER MODULE The TMPR3922AU has a Timer module with the following features. Real Time Clock (RTC) and Timer 43-bit counter (30.517 s granularity); maximum uninterrupted time = 3104 days 43-bit alarm register (30.517 s granularity) 16-bit periodic timer (0.868 s granularity); maximum timeout = 56.8 ms interrupts on alarm, timer, and prior to RTC roll-over 5 ...
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... Thus, when designing products which include this device, ensure that the recommended operating Conditions for the device are always adhered to. Symbol V DDH V V DDL, DDLS V DDP STG P D Condition DDH V DDLS OPR TMPR3922AU (GND) SS Rating Unit V -0 -0 0.5 DDH - 55 to 125 (GND) SS MIN. TYP. MAX. 3.0 3 ...
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... DDH 3.0V -8mA V DDH 3.0V -8mA DDH 3.0V -16mA V DDH 3.0V -16mA DDH MAX DDH VIN = V DDH TMPR3922AU and V = 2.7V 0.2V) DDL DDLS TYP. MAX. Unit – 150 – 100 A – 60 110 A – – 0.8 V +0.3 V – 0.2 V – ...
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... External capacitors Please note that there are some consideration on the location of the external crystal as follows. 1. Please place the crystal as close to the TMPR3922AU as possible. 2. Please place the crystal as far from data bus lines as possible. 3. Please surround the crystal area with GND. ...
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... IN OUT Please note that there are some consideration on the location of the external crystal as follows. 1. Please place the crystal as close to The TMPR3922AU as possible. 2. Please place the crystal as far from data bus lines as possible. 3. Please surround the crystal area with GND. C6MOUT ’ ...
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... Parameter External capacitors Please note that there are some consideration on the location of the external crystal as follows. 1. Please place the crystal as close to The TMPR3922AU as possible. 2. Please place the crystal as far from data bus lines as possible. 3. Please surround the crystal area with GND. ...
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... TMPR3922AU TIMING 6.5.1 DEFINITION OF AC SPECIFICATION 0.8 Delay OUTPUTS 0.8V CC INPUTS 0.2V CC 6.6 AC CHARACTERISTICS The following operating conditions apply to all values specified in this section 70º 3.3 0.3V DDH <Memory Interface> Item Parameter 1 DCLKOUT high time 2 DCLKOUT low time 3 DCLKOUT period 4 Delay DCLKOUT to ALE 4 Delay DCLKOUT to ALE 2 ...
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... Delay DCLKOUT to MCS1-0* 4 Delay DCLKOUT to MCS1-0* 5 D[31 : 16] to DCLKIN Setup time 6 D[31 : 16] to DCLKIN Hold time 5 D[15:0] to DCLKIN Setup time 6 D[15:0] to DCLKIN Hold time 7 DCLKOUT to DCLKIN Board Delay time TMPR3922AU Rising / Falling MIN. MAX. – – – 1.5 Rising – Falling – Rising – ...
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... DCLKOUT MEMORY OUTPUTS DCLKIN MEMORY INPUTS DCLKOUT DCLKIN Memory Output and Clock Timing 5 Memory Input Timing 7 DCLKOUT to DCLKIN TMPR3922AU 4 6 2-FEB-1999 ...
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... CHIFS to CHICLK Falling Setup time(Slave) 9 CHIFS to CHICLK Falling Hold time(Slave) 5 CHIDIN to CHICLK Rising Setup time(Slave) 6 CHIDIN to CHICLK Rising Hold time(Slave) 8 CHIDIN to CHICLK Falling Setup time(Slave) 9 CHIDIN to CHICLK Falling Hold time(Slave) TMPR3922AU Rising / Falling MIN. MAX. 100 – – – 100 – – ...
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... CHICLK CHI OUTPUTS CHI Output and Clock Timing (CHITXEDGE=1) CHICLK CHI INPUTS CHICLK CHI OUTPUTS CHI Output and Clock Timing (CHITXEDGE=0) CHICLK CHI INPUTS CHI Input Timing (CHIRXEDGE=1) 8 CHI Input Timing (CHIRXEDGE=0) TMPR3922AU 2-FEB-1999 ...
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... SIBMCLK SIBSCLK SIBSCLK SIB OUTPUTS SIBDIN Rising / Falling – – – Rising Falling Rising Falling Rising Falling – – SIB CLK Timing SIB Timing TMPR3922AU MIN. MAX. 20 – 20 – 50 – 10 – 10 – – 10 – – 10 – 20 – 0 – ...
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... SPIOUT SPIIN Rising / Falling – – – Rising Falling Rising Falling – – – – SPI Timing (PHAPOL= SPI Timing (PHAPOL=0) TMPR3922AU MIN. MAX. Unit 120 ns – 120 – ns 250 – – – – – ...
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... Parameter 1 VSTANDBY to PON* Rising 2 VSTANDBY to ONBUTN delay time VSTANDBY PON ONBUTN <CPU RESET> Item Parameter 1 CPURES* low time CPURES* Rising / Falling – – Rising / Falling – 1 TMPR3922AU MIN. MAX. Unit 50 ms – 2 – s MIN. MAX. Unit 10 ns – 2-FEB-1999 / 43 45 ...
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... PACKAGE DIMENSION 7.1 TMPR3922AU LQFP208-P-2828-0.50A TMPR3922AU Unit : mm 2-FEB-1999 / 44 45 ...
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... TMPR3922AU 2-FEB-1999 / 45 45 ...