k6r4008c1c-e Samsung Semiconductor, Inc., k6r4008c1c-e Datasheet

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM Document Title 512Kx8 Bit High Speed Static RAM(5V Operating). Operated at Extended and Industrial Temperature Ranges. Revision History Rev No. History Rev. 0.0 Initial release with Preliminary. Rev. 1.0 1.1 Removed Low power Version. 1.2 Removed Data Retention Characteristics. 1.3 Changed I to 20mA SB1 Rev ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM 512K x 8 Bit High-Speed CMOS Static RAM FEATURES • Fast Access Time 10,12,15ns(Max.) • Low Power Dissipation Standby (TTL) : 60mA(Max.) (CMOS) : 10mA(Max.) Operating K6R4008C1C-10 : 170mA(Max.) K6R4008C1C-12 : 160mA(Max.) K6R4008C1C-15 : 150mA(Max.) • Single 5.0V 10% Power Supply • TTL Compatible Inputs and Outputs • ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM PIN CONFIGURATION (Top View I I 36-SOJ Vcc 9 Vss PIN FUNCTION Pin Name Pin Function Address Inputs ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS* Parameter Supply Voltage Ground Input High Voltage Input Low Voltage * The above parameters are also guaranteed at extended and industrial temperature range (Min) = -2.0V a.c(Pulse Width 8ns) for I IL *** V (Max 2.0V a.c (Pulse Width 8ns) for I IH ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM AC CHARACTERISTICS ( TEST CONDITIONS* Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads * The above test conditions are also applied at extended and industrial temperature range. Output Loads(A) ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM WRITE CYCLE* Parameter Symbol Write Cycle Time t WC Chip Select to End of Write t CW Address Set-up Time t AS Address Valid to End of Write t AW Write Pulse Width(OE High Write Pulse Width(OE Low) t WP1 Write Recovery Time t WR ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) Address High-Z Data in Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS WE High-Z Data in Data out TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out (OE= Clock CW( WP(2) AS( ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high ...

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... K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM PACKAGE DIMENSIONS 36-SOJ-400 #36 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 +0.004 0.017 0.95 -0.002 ( ) 0.0375 44-TSOP2-400BF #44 #1 18.81 MAX 0.741 18.41 0.10 0.725 0.004 0.10 0.30 0.05 0.805 ( ) 0.004 0.012 0.032 0.002 #19 #18 23.90 MAX 0.941 23.50 0.12 0.925 0.005 ( ( +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #23 11.76 0.20 0.463 0.008 #22 1.00 1.20 0.10 MAX 0.039 0.047 0.004 0.10 0.05 0.004 MIN 0 ...