k6r4004c1d Samsung Semiconductor, Inc., k6r4004c1d Datasheet - Page 8

• Manufacturer Part Number: k6r4004c1d
• Description: 1m X 4 Bit High-speed Cmos Static Ram
• Manufacturer: Samsung Semiconductor, Inc.

FUNCTIONAL DESCRIPTION
* X means Don
K6R4004C1D
CS
H
L
L
L
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
3. t
4. t
5. t
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
′
t Care.
ends at the earliest transition CS going high or WE going high. t
output must not be applied because bus contention can occur.
CW i
AS
WR
is measured from the address valid to the beginning of write.
is measured from the end of write to the address change. t
s measured from the later of CS going low to end of write.
WE
X
H
H
L
OE
X*
H
X
L
Output Disable
Not Select
Mode
Read
Write
- 8 -
WR
WP
applied in case a write ends as CS or WE going high.
is measured from the beginning of write to the end of write.
I/O Pin
High-Z
High-Z
D
D
OUT
IN
PRELIMINARY
CMOS SRAM
Supply Current
I
SB
I
I
I
, I
CC
CC
CC
SB1
July 2004
Rev. 2.0