wjce6354sl9g6882208 ETC-unknow, wjce6354sl9g6882208 Datasheet

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wjce6354sl9g6882208

Manufacturer Part Number
wjce6354sl9g6882208
Description
Diversity Enabled Nordig Unified Dvb-t Cofdm Terrestrial Demodulator For Pc-tv And Hand-held Digital Tv Dtv
Manufacturer
ETC-unknow
Datasheet
Diversity Enabled Nordig Unified DVB-T
COFDM Terrestrial Demodulator for
PC-TV and Hand-held Digital TV (DTV)
Data Sheet
Features
Compliant with ETSI 300 744 DVB-T, Unified
Nordig and DTG performance specifications
Diversity enabled multi-tuner solution.
High performance with fast fully blind acquisition
and tracking capability
Low power consumption: less than 0.32 W, and
eco-friendly standby and sleep modes
Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM
Superior single frequency network performance
Fast AGC to track out signal fades
Advanced Doppler tracking capability
Enhanced frequency capture range to include
triple offsets
External 4 MHz clock or single low-cost
20.48 MHz crystal, tolerance up to +/-200 ppm
Automatic mode (2 K/8 K), guard and spectral
inversion detection
Very low driver software overhead due to on-chip
state-machine control
Novel RF level detect facility via a separate ADC
Intel Corporation
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Figure 1 - Block Diagram
1
Copyright © 2006 Intel Corporation. All rights reserved.
DJCE6354 882130
WJCE6354 882209
DJCE6354 S L9G2 882132
WJCE6354 S L9G6 882208
Pre and post Viterbi-decoder bit error rates, and
uncorrectable block count
Ordering Information
*Pb Free Matte Tin
64 Pin LQFPTrays
64 Pin LQFP*Trays
64 Pin LQFP Tape and Reel
64 Pin LQFP*Tape and Reel
D55753-001
February 2006

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wjce6354sl9g6882208 Summary of contents

Page 1

Diversity Enabled Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV) Data Sheet Features • Compliant with ETSI 300 744 DVB-T, Unified Nordig and DTG performance specifications • Diversity enabled multi-tuner solution. • High performance with ...

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Applications • Digital terrestrial set-top boxes • Integrated digital televisions • Personal video recorders • PC-TV receivers • Portable applications Description The CE6354 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds, with margin, the ...

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Pin & Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table 1 - Pin Names - numeric ...

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Pin & Package Details 1.1 Pin Outline Figure 2 below shows the basic, non-diversity, pin functions of the CE6354. The device can effectively be set up in seven different pin configurations, so for brevity only this version is shown. ...

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Pin Allocation Pin Function Pin 1 Vss 17 SADD1 2 Vdd 18 SADD0 3 Vss 19 CVdd 4 CLK1 20 Vss 5 DATA1 21 PLLVdd 6 IRQ/Dv4/Dv0 22 PLLGND 7 CVdd 23 XTI 8 Vss 24 XTO 9 RESET ...

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CVdd 37 MICLK CVdd 39 MOCLK/DvClk CVdd 59 MOSTRT CVdd 64 MOVAL/DvVal DATA1 5 OSCMODE DATA2/GPP1 36 PLLGND Table 2 - Pin Names - alphabetical order (continued) 1.3 Pin Description Pin Description Table Pin No Name MPEG pins 47 MOSTRT ...

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Pin Description Table (continued) Pin No Name 35 CLK2/GPP0 36 DATA2/GPP1 42 AGC1 41 AGC2/GPP2 43 GPP(3) 9 RESET 27 OSCMODE 26 PLLTEST Analog inputs 30 VIN 31 VIN 34 RFLEV Supply pins 21 PLLVdd 22 PLLGnd 7, 19, 37, ...

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Functional Description A functional block diagram of the CE6354 OFDM demodulator is shown in Figure 3. This accepts an IF analog signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and ...

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The FSM controller shown in Figure 3 controls both the demodulator and the FEC. It also drives the 2-wire bus to the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the received ...

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The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking. The AGC is free running during OFDM channel changes and locks to the new channel while the tuner ...

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Common Phase Error Correction This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the tuner phase noise on system performance. 2.10 Channel Equalization This consists of two parts. ...

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Viterbi Decoder The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream. The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the ...

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Diversity Operation of CE6354 The CE6354 demodulator can be used as a stand-alone system, but is designed primarily for use as part of a multi- receiver system in which two or more tuners, each with their own aerial, are ...

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Figure 6 - Outline of Dual Diversity/Play-and-Record System Although the two functions are very different, this one hardware design can easily be used in either mode just by setting the appropriate diversity register bits, and of course using appropriate software ...

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Pin Function Pin Function 4 Dv1 15 31 VIN 5 Dv0 16 32 AGnd Table 3 - Pin Names Mode A - diversity first or last device in chain (continued) 1. Can be defined as either an input or output ...

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Pin Function Pin Function 6 IRQ 22 PLLGND 7 CVdd 23 XTI 8 Vss 24 XTO 9 RESET 25 Vss 10 SLEEP 26 PLLTEST 11 STATUS 27 OSCMODE 12 N/C 28 AVdd 13 Vdd 29 AGnd 14 Vss 30 VIN ...

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Interfaces 4.1 2-Wire Bus 4.1.1 Host The primary 2-wire bus serial interface uses pins: • DATA1 (pin 5) serial data, the most significant bit is sent first. • CLK1 (pin 4) serial clock. The 2-wire bus address is determined ...

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Examples of 2-Wire Bus Messages KEY Italics Write operation - as a slave receiver: S DEVICE W A RADD ADDRESS (n) Read operation - CE6354 as a slave transmitter: S DEVICE R A DATA ADDRESS (reg ...

Page 23

Parameter CLK clock frequency (Primary) Bus free time between a STOP and START condition. Hold time (repeated) START condition. LOW period of CLK clock. HIGH period of CLK clock. Set-up time for a repeated START condition. Data hold time (when ...

Page 24

Timing conditions Parameter Minimum Diversity clock period t 22.06 DvrP Diversity setup time t DvrSU Diversity hold time t DvrH Table 8 - Diversity Bus Timing 4.3 MPEG 4.3.1 Data Output Header Format Transport Packet Header 0 TEI MDO[7] Figure ...

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MPEG Data Output Signals The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be ...

Page 26

MOCLKINV 1 = Delay conditions Parameter Maximum Data output delay t 3.0 D Setup Time t 7.0 SU Hold Time t 7.0 H MOCLK MDO } MOSTRT MOVAL BKERRB BKERR 4.3.5 MOCLKINV 0 = MDOSWAP = 0 Parameter Maximum ...

Page 27

Electrical Characteristics 5.1 Recommended Operating Conditions Parameter Power supply voltage: Power supply current: 3 Input clock frequency CLK1 primary serial clock frequency Ambient operating temperature 1. Current from the 3.3 V supply will be mainly dependent on the external ...

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DC Electrical Characteristics DC Electrical Characteristics Parameter Conditions Operating periphery voltage core 1 Supply current 1.62>CVDD>1.98 Supply current sleep mode Outputs Output levels IOH 2mA 3.0>VDD>3.6 IOL 2mA 3.0>VDD>3.6 IOL 6mA 3.0>VDD>3.6 Output capacitance Not including track MDO(7:0), MOVAL, ...

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Selection of External Components The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is greater than unity. Correct selection of the two capacitors is very important and the following method ...

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Calculating Crystal Power Dissipation To calculate the power dissipated in a crystal the following equation can be used Equation 8 power dissipated in crystal at resonant frequency (W) ...

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Oscillator/Clock Application Notes • On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other signal tracks must not be allowed to cross through this area. The component tracks should ...

Page 32

Application Circuit CE6354 Figure 16 - Typical Application Circuit 32 Intel Corporation Data Sheet ...

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