ta1317ang TOSHIBA Semiconductor CORPORATION, ta1317ang Datasheet - Page 18

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ta1317ang

Manufacturer Part Number
ta1317ang
Description
Deflection Processor Ic For Tv
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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becomes a transmitter.
sub-address.
I
2
C BUS Conditions
At the moment of the first acknowledge, the master transmitter becomes a receiver and the slave receiver
The Stop condition is generated by the master.
In this transmission method, sub-addresses are incremented automatically and data is set from the specified
Data Transmit Format 1
Data Transmit Format 2
Data Receive Format
Optional Data Transmit Format: Automatic Increment Mode
Low level input voltage
High level input voltage
Low level output voltage at 3 mA sink current
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Capacitance for each I/O pin
SCL clock frequency
Hold time START condition
Low period of SCL clock
High period of SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP and START condition
S: Start condition
S
S
S
S
MSB
MSB
MSB
Slave address
Slave address
Slave address
Slave address
Characteristics
7 bit
7 bit
7 bit
0 A
0 A
1 A
0
A: Acknowledge
A 1
MSB
MSB
MSB
・・・・・・
Receive data
Sub address
Sub address
Sub address
8 bit
8 bit
7 bit
Sub address
t
t
Symbol
t
t
t
A
A
A
HD;STA
SU;STA
HD;DAT
SU;DAT
SU;STO
t
V
t
f
t
HIGH
LOW
V
BUF
V
SCL
OL1
C
18
MSB
I
IH
IL
P
i
A
i
Transmit data
Transmit data
MSB
Transmit data 1
A
9 bit
Min
−10
100
250
2.7
4.0
4.7
4.0
4.7
4.0
4.7
Transmit data n
8 bit
0
0
0
Typ.
A P
A
P: Stop condition
・・・・
・・・・・・
Max
Vcc
100
1.5
0.4
10
10
A P
MSB
Transmit data 2
Unit
kHz
µA
pF
µs
µs
µs
µs
ns
ns
µs
µs
V
V
V
8 bit
TA1317ANG
A P
2005-08-18

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