ta1360afg TOSHIBA Semiconductor CORPORATION, ta1360afg Datasheet - Page 97
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ta1360afg
Manufacturer Part Number
ta1360afg
Description
Ycbcr/ypbpr Signal And Sync Processor For Digital Tv, Progressive Scan Tv And Double Scan Tv
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TA1360AFG.pdf
(110 pages)
Available stocks
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Quantity
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Part Number:
TA1360AFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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HA03 Polarity detection
HA04 Sync input threshold
Note
range
amplitude
Characteristics
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
Set subaddress (00) data to 40H.
Input signal B (as shown in the figure below) to TP50 pin.
Decrease signal B duty from 10% (to shorter negative polarity period) and measure signal B
duty (HD
Increase signal B duty from 10% (to longer negative polarity period) and measure signal B duty
(HD
Further increase signal B duty (to longer negative polarity period) and measure signal B duty
(HD
Decrease signal B duty from 90 % (to shorter negative polarity period) and measure signal B
duty (HD
Duty = A/B × 100% (0 to 100%)
Set subaddress (00) data to 82H, and TEST mode to 01.
Connect variable power supply to #53 via 20-kΩ resistor.
Set variable power supply voltage to 0 V, and measure #53 voltage. (SYNC_TIP_00) Also
check that #34 voltage is set to Low (GND level).
Increase variable power supply voltage so that #34 voltage becomes High (VCC level).
Measure #53 voltage. (SYNC_OFF_00)
Calculate the following equation to determine SYNC input separation level at SYNC separation
level is 00. V
Change SYNC separation level to 01, 10, and 11. Calculate following equations to determine
VthS01, VthS10, and VthS11.
#34
(SYNC output mode)
Signal B
DUTY2
DUTY3
#53
V
V
V
DUTY1
DUTY4
thS01
thS10
thS11
) when #39 (FBP input) phase changes in relation to signal B.
) when #50 input signal phase no longer locks with that of #37 (H-OUT).
(= 286 mVp-p)
thS00
= (SYNC_OFF_01 − SYNC_TIP_01)/0.286 × 100
= (SYNC_OFF_10 − SYNC_TIP_10)/0.286 × 100
= (SYNC_OFF_11 − SYNC_TIP_11)/0.286 × 100
) when #50 input signal phase no longer locks with that of #37 (H-OUT).
) when #39 (FBP input) phase changes in relation to signal B.
= (SYNC_OFF_00 − SYNC_TIP_00)/0.286 × 100
40IRE
A
97
31.75 µs
Test Conditions
B
1H
1.5 V
Sync tip level
Sync separation level
0.08H
TA1360AFG
2005-08-18
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