a42l2604 AMIC Technology Corporation, a42l2604 Datasheet - Page 3

• Manufacturer Part Number: a42l2604
• Description: 4m X 4 Cmos Dynamic Ram With Edo Page Mode - Amic Technology
• Manufacturer: AMIC Technology Corporation

Selection Guide
Functional Description
The A42L2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
are routed through 4 common I/O pins, with RAS , CAS ,
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (t
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
PRELIMINARY
RAS and CAS are used to strobe the row address and the
CAS , whichever occurs later. The data inputs and outputs
CAS . While holding RAS low, CAS can be toggled to
WE and OE controlling the in direction.
Symbol
t
t
t
t
t
t
RAC
CAC
OEA
AA
RC
PC
cp
). Since data can be output after CAS goes high,
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
(June, 2002, Version 0.3)
Description
2
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
maintaining
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid V
surges.
CAS high. Memory cell data will retain its correct state by
-45
45
20
12
12
76
18
power
IH
and
during Power-On to avoid current
AMIC Technology, Inc.
-50
50
22
13
13
84
20
A42L2604 Series
accessing
all
Unit
ns
ns
ns
ns
ns
ns
2048(2K)