h5ps2g43afr Hynix Semiconductor, h5ps2g43afr Datasheet - Page 39

• Manufacturer Part Number: h5ps2g43afr
• Description: Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.1 / November 2008
tracting 0.02 x tCK (avg) from it, whereas if an input clock has a worst case tCH (avg) of 0.52, the tAOF,
max should be derated by adding 0.02 x tCK (avg) to it. Therefore, we have;
tAOF, min (derated) = tAC, min - [0.5 - Min(0.5, tCH (avg), min)] x tCK (avg)
tAOF, max (derated) = tAC, max + 0.6 + [Max(0.5, tCH (avg), max) - 0.5] x tCK (avg)
or
tAOF, min (derated) = Min (tAC, min, tAC, min - [0.5 - tCH (avg), min] x tCK (avg))
tAOF, max (derated) = 0.6 + Max (tAC, max, tAC, max + [tCH (avg), max - 0.5] x tCK (avg))
where tCH (avg), min and tCH (avg), max are the minimum and maximum of tCH (avg) actually measured
at the DRAM input balls.
Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT (duty) and
tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter
table and are not derated. Thus the final derated values for tAOF are;
tAOF, min (derated_final) = tAOF, min (derated) + {- tJIT (duty), max - tERR(6-10per),max}
tAOF, max (derated_final) = tAOF, max (derated) + {- tJIT (duty), min - tERR(6-10per),min}
H5PS2G43AFR
H5PS2G83AFR
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