adc-44d ETC-unknow, adc-44d Datasheet - Page 33

• Manufacturer Part Number: adc-44d
• Description: Multi-function Analogue Input/output Card
• Manufacturer: ETC-unknow

Chapter 5
In its simplest mode an ADC cycle is triggered by writing to Base + 5 with bits
6 and 7 of the ADC CONTROL register set to zero (default condition).
A typical sequence of events to acquire data in this mode would be:
In the second mode set Base + 4 bit 6 high, and bit 7 low and initiate the first
conversion by writing to Base + 5. The ADC is then automatically re-triggered
when data from the previous sample is read
In the third mode the ADC is re-triggered when Timer 2 overflows. This mode
is best used for DMA or INTERRUPT operation. It is selected by setting Base +
4 bit 6 high, and bit 7 high. The sequence would be:
Blue Chip Technology Ltd.
Select the mode by setting Base + 4 bit 6 high, and bit 7 high.
Set the input gain and type by writing to bits 0 to 2 of Base + 4.
Program Timers 0 and 2 to give the required output rate.
If DMA operation is required program the DMA controller and set bit 4 of
Base + 4.
Enable the Timer output by setting bit 3 of Base + 4.
Select the mode by writing the value 0 to bits 3 to 7 of Base + 4.
Set the input gain and type by writing to bits 0 to 2 of Base + 4.
Write the required input channel number to the upper 4 bits of Base + 6.
Start the conversion with a write to Base + 5.
Monitor bit 0 of Base + 6 (ADC BUSY) until it goes LOW indicating data
is available following a conversion cycle.
Read Base + 3 for the data low byte.
Read Base + 3 again for the data high byte.
Operation of the Card
01270170.doc
Page 25