A43L2616AG-6 AMICC [AMIC Technology], A43L2616AG-6 Datasheet - Page 10

• Manufacturer Part Number: A43L2616AG-6
• Description: 1M X 16 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Mode Register Filed Table to Program Modes
Register Programmed with MRS
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µ s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
PRELIMINARY
A9
A8
0
1
Address
0
0
1
1
Function
A7
Write Burst Length
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
0
1
0
1
(Note 1)
Test Mode
Mode Register Set
Single Bit
BS0, BS1
Length
Burst
(November, 2004, Version 0.0)
RFU
Vendor
Type
(Note 2)
Only
Use
A11, A10
RFU
A6
0
0
0
0
1
1
1
1
A5
0
1
0
1
1
0
0
1
CAS Latency
W.B.L
A9
A4
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
A8
2
3
-
TM
9
A7
A3
0
1
Burst Type
A6
Sequential
Interleave
CAS Latency
Type
A5
A2
0
0
0
0
1
1
1
1
A4
AMIC Technology, Corp.
A1
0
0
1
1
0
0
1
1
A3
BT
A0
0
1
0
1
0
1
0
1
Burst Length
Reserved
Reserved
Reserved
256(Full)
BT=0
A2
A43L2616A
1
2
4
8
Burst Length
A1
Reserved
Reserved
Reserved
Reserved
BT=1
1
2
4
8
A0