M25P05-AVDW6G NUMONYX [Numonyx B.V], M25P05-AVDW6G Datasheet - Page 13

• Manufacturer Part Number: M25P05-AVDW6G
• Description: 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

M25P05-A
4.5
4.5.1
4.5.2
4.5.3
4.5.4
Status register
The status register contains a number of status and control bits, as shown in
can be read or set (as appropriate) by specific instructions.
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write status
register, program or erase cycle.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
BP1, BP0 bits
The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against program and erase instructions.
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal
allow the device to be put in the hardware protected mode. In this mode, the non-volatile bits
of the status register (SRWD, BP1, BP0) become read-only bits.
Operating features
Table
6, that
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