M25P05-AVDW6G NUMONYX [Numonyx B.V], M25P05-AVDW6G Datasheet - Page 27

• Manufacturer Part Number: M25P05-AVDW6G
• Description: 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

M25P05-A
6.7
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
There is no address roll-over; when the highest address (0FFFFh) is reached, the
instruction should be terminated.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip
Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read
data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence
1. Address bits A23 to A16 must be set to 00h.
S
C
D
Q
S
C
D
Q
0
and data-out sequence
7
32 33 34
1
High Impedance
6
2
Instruction
Dummy byte
5
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
5
2
6
1
7
0
23
8
MSB
7
22 21
Figure 13.
9 10
6
24-bit address
DATA OUT 1
5
C
, during the falling edge of Serial Clock (C).
4
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
Instructions
0
AI04006
MSB
7
27/52